HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 395

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Testability—Intel
7.1.12
7.2
July 2009
Order Number: 318378-005US
Boundary Scan Register
The following requirements apply to those interfaces that continue to support boundary
scan (bscan) or the miscellaneous I/O signals.
Extended Debug Port (XDP)
The Extended Debug Port is covered in the Debug Port Design Guide for Intel
Series Chipset Based Platforms.
®
• Each signal or clock pin (with the exception of the TAP specific pins TCK, TDI, TDO,
• Internal Signals which control the direction of I/O pins shall also have associated
• Each Output pin (with the exception of TDO) shall be able to be driven to a tristate
5100 MCH Chipset
TMS, & TRST#) will have an associated Boundary-Scan Register Cell. Differential
Driver or Receiver Pin Pairs that cannot be used independently shall be considered
a single pin (i.e., one Boundary-Scan Register Cell after the differential receiver).
Boundary- Scan Register Cells.
condition for HIGHZ test.
Intel
®
5100 Memory Controller Hub Chipset
®
Datasheet
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