HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 198

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.9.5
3.9.5.1
3.9.5.2
Intel
Datasheet
198
®
5100 Memory Controller Hub Chipset
Memory Map Registers
TOLM - Top Of Low Memory
This register defines the low MMIO gap below 4 GB. See
Memory Interleave Range.”
Whereas the MIR.LIMITs are adjustable, TOLM establishes the maximum address below
4 GB that should be treated as a memory access. TOLM is defined in a 256 MB
boundary.
This register must not be modified while servicing memory requests.
MIR[1:0]: Memory Interleave Range
These registers define each memory branch’s interleave participation in processor-
physical (A) space.
The MC uses all 39 physical address bits for DRAM memory addressing. However, when
the next-most significant bit is set in the LIMIT field of the MIR[1:0] registers defined
below, the rest of the bits in the LIMIT field are ignored, and the LIMIT field is
interpreted as 512 GB.
The MIR addresses A[38:28] in multiples of 256 MB boundaries. The MMIO gap is
defined as 4 GB - TOLM or mathematically (10H-TOLM.TOLM)x256 MB
Each MIR register defines a range. If the processor-physical address falls in the range
defined by an MIR, the “way” fields in that MIR define channel participation in the
interleave. The way-sensitive address bit is A[6]. For a MIR to be effective, WAY0 and
WAY1 fields can not both be set to 0b. Matching addresses participate in the
corresponding ways.
Compensation for MMIO gap size is performed by adjusting the limit of each range
upward if it is above TOLM as shown in
by MIR[i] if.”
Device:
Function:
Offset:
15:12
11:0
Bit
Attr
RW
RV
16
1
6Ch
Default
000h
1h
TOLM: Top Of Low Memory
This register defines the maximum DRAM memory address that lies below 4
GB. It does not denote the actual low MMIO gap but the upperbound of the
system low memory.
Addresses equal to or greater than the TOLM, and less than 4 GB, are
decoded as low MMIO, MMCFG (if map within this range by HECBASE),
chipset, interrupt/SMM and firmware as described in
Address Map.”
(except for the VGA region when enabled and PAM gaps).
Configuration software should set this field either to maximize the amount of
memory in the system (same as the top MIR.LIMIT), or to minimize the
allocated space for the lower PCI memory (low MMIO) plus 32 MB (chipset/
interrupt/SMM and firmware) at a 256 MB boundary.
This field must be set to at least 1h, for a minimum of 256 MB of DRAM. The
smallest gap between TOLM and 4 GB (for low MMIO, MMCFG, chipset,
interrupt/SMM and firmware) is 256 MB because the largest value of TOLM is
0Fh. TOLM cannot be set higher than the total amount of physical memory.
This field corresponds to A[31:28]. Setting of “1111” corresponds to 3.75 GB
DRAM, and so on down to “0001” corresponds to 0.25 GB DRAM. “0000”
setting is illegal and a programming error.
Reserved
All accesses less than the TOLM are treated as DRAM accesses
Table 66, “Interleaving of Address Is Governed
Intel
®
Description
5100 MCH Chipset—Register Description
Section 3.9.5.2, “MIR[1:0]:
Order Number: 318378-005US
Section 4.0, “System
July 2009