HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 14

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

7.0
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5100 Memory Controller Hub Chipset
Testability.............................................................................................................. 386
7.1
7.2
Ballout and Package Information ........................................................................... 396
8.1
8.2
8.3
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Power-Up ................................................................................................................60
PWRGOOD...............................................................................................................61
Hard Reset ..............................................................................................................61
RESETI# Retriggering Limitations ...............................................................................62
Conceptual Intel
Type 1 Configuration Address to PCI Address Mapping...................................................71
Intel
PCI Express* Configuration Space ............................................................................ 112
PCI Hot Plug* Interrupt Flow .................................................................................... 154
Intel
Flow ..................................................................................................................... 229
Detailed Memory System Address Map ...................................................................... 260
Interrupt/SMM Region ............................................................................................. 267
System I/O Address Space ...................................................................................... 276
Representative Memory System 32 GB Mode.............................................................. 281
Connection of DIMM Serial I/O Signals ...................................................................... 285
XAPIC Address Encoding.......................................................................................... 292
PCI Hot Plug* Interrupt Flow .................................................................................... 300
Interrupt Swizzle .................................................................................................... 304
No Interrupt Swizzle ............................................................................................... 305
Intel
x4 PCI Express* Bit Lane ......................................................................................... 309
Intel
PCI Express* High Performance x16 Port ................................................................... 311
PCI Express* Packet Visibility By Physical Layer.......................................................... 313
PCI Express* Elastic Buffer (x4 Example)................................................................... 314
PCI Express* Deskew Buffer (4x Example)................................................................. 315
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JTAG Port ....................................................................................................... 386
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
7.1.6
7.1.7
7.1.8
7.1.9
7.1.10 Bypass Register.................................................................................... 393
7.1.11 Device ID Register ................................................................................ 393
7.1.12 Boundary Scan Register......................................................................... 395
Extended Debug Port (XDP) .............................................................................. 395
Intel
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Package Information ........................................................................................ 432
5100 Memory Controller Hub Chipset DMA Error/Channel Completion Interrupt Handling
5100 Memory Controller Hub Chipset-based System Block Diagram .......................32
5100 Memory Controller Hub Chipset Signal Diagram 32 GB Mode .........................57
5100 Memory Controller Hub Chipset Signal Diagram 48 GB Mode .........................58
5100 Memory Controller Hub Chipset Clock and Reset Requirements .....................59
5100 Memory Controller Hub Chipset Implementation of SRID and CRID Registers ..95
5100 Memory Controller Hub Chipset to ICH9R Enterprise South Bridge Interface .. 306
5100 Memory Controller Hub Chipset PCI Express* General Purpose Ports ............ 310
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5100 Memory Controller Hub Chipset Ballout ............................................. 396
5100 Memory Controller Hub Chipset Ballout ............................................. 397
TAP Signals.......................................................................................... 386
Accessing TAP Logic .............................................................................. 387
Reset Behavior of TAP ........................................................................... 389
Clocking TAP ........................................................................................ 389
Accessing Instruction Register ................................................................ 389
Accessing Data Registers ....................................................................... 391
Public TAP Instructions .......................................................................... 391
Public Data Instructions ......................................................................... 392
Public Data Register Control ................................................................... 393
7.1.11.1 Device ID Register................................................................... 394
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5100 Memory Controller Hub Chipset PCI Configuration Diagram ..........69
Intel
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5100 MCH Chipset—Contents
Order Number: 318378-005US
July 2009