HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 368

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.22.6
5.22.6.1
5.22.6.2
5.22.6.3
5.22.6.4
5.22.6.5
5.22.6.6
5.22.6.7
5.22.6.8
Intel
Datasheet
368
®
5100 Memory Controller Hub Chipset
High Frequency Clocking Support
Spread Spectrum Support
Intel
frequency modulation technique for EMI reduction. Instead of maintaining a constant
frequency, SSC modulates the clock frequency/period along a predetermined path, i.e.,
the modulation profile. The Intel
modulation frequency of 30 kHz with a down spread of 0.5%.
Stop Clock
PLLs in the Intel
Jitter
The DDR UI clocks are produced by PLLs that multiply the DDRCLK frequency by 24.
The PCI Express* phit clocks are produced by PLLs that multiply the PECLK frequency
by 25. These multi-GHz phit clocks require ultra-clean sources, ruling out all but
specifically-crafted low-jitter clock synthesizers.
External Reference
An external crystal oscillator is the preferred source for the PLL reference clock. A
spread spectrum frequency synthesizer that meets the jitter input requirements of the
PLL is acceptable.
PLL Lock Time
All PLLs should be locked by PWRGOOD signal assertion. The reference clocks must be
stable 1 ms before the assertion of the PWRGOOD signal. The assertion of the
PWRGOOD signal initiates the PLL lock process. External clocks dependent on PLLs are
GPIO clock and SMBus clock. Many JTAG private registers are dependent on core PLL-
generated clocks.
Other PLL Characteristics
The PLL VCOs oscillate continually from power-up. The PLL output dividers consistently
track the VCO, providing pulses to the clock trees. Logic that does not receive an
asynchronous reset can thus be reset “synchronously”.
A “locked” PLL will only serve to prove that the feedback loop is continuous. It will not
prove that the entire clock tree is continuous.
Analog Power Supply Pins
The Intel
Vcc and Analog Vss pad and external LC filter. Therefore, there will be external LC
filters for the Intel
to board Vss. The ground connection of the filter will be routed through the package
and grounded to on-die Vss.
I/O Interface Metastability
PCI Express* can be operated frequency-locked to the core. Flits are fifteen-sixteenths
of the core frequency in 266 MHz mode, three-quarters of the core frequency in 333
MHz mode.
®
5100 MCH Chipset PLLs will support Spread Spectrum Clocking (SSC). SSC is a
®
5100 MCH Chipset incorporates seven PLLs. Each PLL requires an Analog
®
®
5100 MCH Chipset cannot be stopped.
5100 MCH Chipset. IMPORTANT: The filter is NOT to be connected
®
5100 MCH Chipset is designed to support a nominal
Intel
®
5100 MCH Chipset—Functional Description
Order Number: 318378-005US
July 2009