HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 182

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.13.22
3.8.13.23
Intel
Datasheet
182
®
5100 Memory Controller Hub Chipset
ERR2_INT - Internal Error 2 Mask Register
This register enables the signaling of Err[2] when an error flag is set. Note that one and
only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and
MCERR_INT for each of the corresponding bits.
ERR1_INT - Internal Error 1 Mask Register
This register enables the signaling of Err[1] when an error flag is set. Note that one and
only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and
MCERR_INT for each of the corresponding bits
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
7:5
7:5
7:5
Bit
Bit
Bit
4
3
3
2
1
0
4
3
2
1
0
4
3
2
1
0
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
Attr
Attr
Attr
RV
RV
RV
RV
RV
RV
RV
16
2
CCh
16
2
D2h
16
2
D1h
Default
Default
Default
7h
7h
1
1
1
1
1
7h
1
1
1
1
1
1
1
1
1
1
1
Reserved
B5Err2Msk: Address Map Error
B4Err2Msk: SMBus Virtual Pin Error
B3Err2Msk: Coherency Violation Error for EWB
Reserved
B1Err2Msk: DM Parity Error
Reserved
B5Msk: Address Map Error
Reserved
B4Msk: Virtual Pin Port Error
B3Msk: Coherency Violation Error for EWB
Reserved
B1Msk: DM Parity Error
Reserved
B5Err1Msk: Address Map Error
B4Err1Msk: SMBus Virtual Pin Error
B3Err1Msk: Coherency Violation Error
Reserved
B1Err1Msk: DM Parity Error
Intel
®
5100 MCH Chipset—Register Description
Description
Description
Description
Order Number: 318378-005US
July 2009