HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 283

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.2.4.2
Table 89.
5.2.4.3
5.2.4.4
July 2009
Order Number: 318378-005US
Sparing can be forced to activate by setting SPCPC.FORCE and designating the failed
rank in SPCPC.FORCERANK.
This mechanism requires no software support once it has been enabled by designating
the spare rank through the SPCPC.SPRANK configuration register field and enabling
sparing by setting the SPCPC.SPAREN configuration bit. Hardware will detect the
threshold-initiated fail, accomplish the copy, and off-line the “failed” DIMM rank once
the copy has completed. This is accomplished autonomously by the memory control
subsystem. The SPCPS.SFO configuration bit is set and an interrupt is issued indicating
that a sparing event has completed.
Data Poisoning in Memory
Data Poisoning in memory is defined as all zeroes in the code word (32B) except for the
least significant bytes being FF00FFh. The Intel
location based on the events described in
Memory Poisoning Table
Patrol Scrubbing
To enable this function, the Memory Controller (MC), MC.SCRBEN configuration bit
must be set. The scrub unit starts at DIMM Rank 0/Address 0 upon reset. Every 16k
core cycles the unit will scrub one cache line and then increment the address one cache
line provided that back pressure or other internal dependencies (queueing, conflicts
etc) do not prolong the issuing of these transactions to DDR. Using this method,
roughly 64 GB of memory behind the Intel
scrubbed every day (estimate). Error logs include RAS/CAS/BANK/RANK.
Normally, one channel is scrubbed in its entirety before proceeding to the other
channel. In the instance of a fail-down to non-redundant operation that off-lines the
channel that was being scrubbed, the scrub pointer merely migrates to the other
channel without being cleared. In this unique instance, the scrub cycles for that
channel are incomplete.
Demand Scrubbing
To enable this function, the MC.DEMSEN configuration bit must be set. Correctable read
data will be corrected to the requestor and scrubbed in memory. This adds an extra
cycle of latency to accomplish the correction. Error logs include RAS/CAS/BANK/RANK.
Normal
Memory Read
Patrol Scrub
Rank Spare
Copy
Event
®
5100 MCH Chipset
Correct Data to be given register
The Intel
error. (Correctable demand data ECC
Error)
Correct Data to be written back to
memory
Correct Data to be written back to
memory and log M16 error. (Correctable
patrolled data ECC error)
Correct Data to be written back to
memory and log M15 error. (Correctable
spare copy data ECC error)
®
Correctable Error
5100 MCH Chipset logs M14
Table 89, “Memory Poisoning Table.”
®
5100 MCH Chipset can be completely
Detects an Uncorrectable and logs a M10 error
(Non-aliased uncorrectable demand data ECC error)
Re-Issue Read to Memory
If error persistent
1.
2.
1.
2.
If error persistent
1.
2.
®
5100 MCH Chipset poisons a memory
Poison the response to requester and log.
Leave data untouched in memory location
Log and Signal M12 Error (Non-Aliased
uncorrectable patrol data ECC error).
Leave data untouched in memory location.
Log and Signal M11 Error (Non Aliased
uncorrectable spare copy data ECC error).
Poison Location in Spare rank
Intel
®
UnCorrectable Error
5100 Memory Controller Hub Chipset
Datasheet
283