HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 52

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 17.
2.4
Table 18.
Intel
Datasheet
52
®
5100 Memory Controller Hub Chipset
PCI Express* Graphics Port Signals (Sheet 2 of 2)
SMBus Interfaces
There are three SMBus interfaces supporting three basic functions. These functions
are:
SMBus Interfaces Signals
PE7RP[3:0]
PE7RN[3:0]
PE7TP[3:0]
PE7TN[3:0]
CFGSMBCLK
CFGSMBDATA
GPIOSMBCLK
GPIOSMBDATA
SPD0SMBCLK
SPD0SMBDATA
Notes:
1.
• System management
• PCI Hot Plug*
• DDR2 DIMM serial presence detect
Signal Name
Signal Name
These signals are Open Drain (OD) and require pull-ups, see Quad-Core and Dual-Core Intel
Processor 5000 Sequence with Intel
Embedded, and Storage Applications – Platform Design Guide or Intel
T9400 and SL9400 and Intel
Embedded Applications – Platform Design Guide for pull-up requirements.
Type
Type
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
PCI Express* Graphics Port Fourth x4, Positive Phase Inbound
PCI Express* Graphics Port Fourth x4, Negative Phase Inbound
PCI Express* Graphics Port Fourth x4, Positive Phase Outbound
PCI Express* Graphics Port Fourth x4, Negative Phase Outbound
Slave SMBus Clock:
SMBus Clock for the slave CFGSMBus interface.
Slave SMBus Data:
SMBus Address/Data for the slave CFGSMBus interface.
PCI SMBus Clock:
PCI Hot Plug* Master VPI, SMBus Clock. The master GPIOSMBus interface only
supports PCI Hot Plug* capabilities; it does not support general purpose I/O
functions.
PCI SMBus Data:
PCI Hot Plug* Master VPI, SMBus Address/Data. The master GPIOSMBus
interface only supports PCI Hot Plug* capabilities; it does not support general
purpose I/O functions.
DDR2 DIMM Channel 0/1 SMBus Clock:
DDR2 DIMM Memory Serial Presence Detect 0, SMBus Clock for the master
SPD0SMBus interface. The SPD0SMBus interface only supports DIMM
configuration/status capabilities; it is not designed for support of general
purpose I/O functions.
DDR2 DIMM Channel 0/1 SMBus Data:
DDR2 DIMM Memory Serial Presence Detect 0, SMBus Address/Data
®
5100 Memory Controller Hub Chipset for Communications and
®
5100 Memory Controller Hub Chipset for Communications,
Intel
Description
Description
®
5100 MCH Chipset—Signal Description
®
Order Number: 318378-005US
Core™2 Duo Processors
®
July 2009
Xeon
®