HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 330

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.17.1
5.17.1.1
Intel
Datasheet
330
®
5100 Memory Controller Hub Chipset
When an I/O driver requests DMA channels, if it wants to use interrupts, it must
provide the DMA Engine driver with the address of its DMA Channel Interrupt Callback
routine, so the DMA Engine interrupt handler can call the Channel Interrupt Callback to
process that channels interrupts.
When a client requests per-port resources, the DMA Engine driver must be able to
determine which post serves the target I/O device. To do this, the requesting driver
must pass the DMA Engine driver the base address of the I/O device. The DMA Engine
device then walks through the per-port register sets looking at
“BR_MEM_BASE[3:2] - Bridge Memory Base Register” on page
“BR_MEM_LIMIT[3:2] - Bridge Memory Limit Register” on page
“BR_PMEM_BASE[3:2] - Bridge Prefetchable Memory Base Register” on page
determine which port serves the I/O device.
If at anytime the DMA Engine device driver gets suspended, it must notify the I/O
drivers and make sure that they have released their DMA Engine resources (such as
clear the REQID register).
Stream/Port Arbitration
Arbitration in the PCI Express* (IOU) cluster(s) occurs at several levels to dispatch
transactions to/from memory. The basic methodology is to guarantee fairness, prevent
starvation and provide some degree of programmability for debug/fine-tuning.
Level 3 - IOU0, IOU1, DMA Arbitration
The Level 3 arbitration shares available bandwidth in the CE by a programmable,
weighted, round robin scheme that scans for requests from the two IOUs (IOU0 and
IOU1) and the DMA Engine optimizing bandwidth and avoiding starvation. The CE has a
bandwidth of 8.53 GB/s (10.6 GB/s) and is proportionately divided based on the
arbitration values defined for DMA, IOU0, IOU1 in the PEXCTRL2[7:2:0], PCI Express*
Control Register 2.
• Level 0 (lowest) - In order to provide better serviceability for high-priority streams
• Level 1: Programmable, weighted round-robin algorithm that alternates between
• Level 1a: Port Arbitration: Ports 4, Port 5, Port 6 and Port 7
• Level 2: Simple round robin algorithm between the Posted, Non-posted queues,
• Level 3 (highest): Programmable, weighted round robin algorithm that connects
from Ports 2 and 3, the Intel
arbitration within IOU0 cluster as follows:
requests from the ESI port and Ports 2/3 and classify them as Posted/Non Posted.
and completions from Level 1 (IOU0) and Level 1a (IOU1) respectively.
the IOU0, IOU1 and DMA Engine with the Coherency Engine (CE) to share the
allocated 8.53/10.6 GB/s bandwidth in each direction.
— The low-priority streams from Ports 2 and 3 are grouped along with Port 0
— The high-priority streams from Ports 2 and 3 are grouped together and round-
— Select one of the requests from IOU1 in a round robin fashion and classify as
(ESI) and round-robin arbitration selects a request from these queues, i.e.,
low-priority (Port 2), low-priority (Port 3) and ESI (Port 0)
robin arbitration proceeds for these requests from high-priority (Port 2) and
high-priority (Port 3)
Posted/Non-Posted
®
5100 MCH Chipset employs a mixed stream/port
Intel
®
5100 MCH Chipset—Functional Description
256,
256,
Order Number: 318378-005US
Section 3.12.0.15,
Section 3.12.0.16,
Section 3.12.0.17,
256, to
July 2009