HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 199

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
Table 66.
3.9.5.3
3.9.6
Note:
July 2009
Order Number: 318378-005US
MIR updates can only occur in the “Reset”, “Ready”, “Fault”, and “Disabled”
configuration register states.
Interleaving of Address Is Governed by MIR[i] if
1. for MIR[0], MIR[i-1] is defined to be 0
AMIR[1:0]: Adjusted Memory Interleave Range
For the convenience of software which is trying to determine the physical location to
which a processor bus address is sent, 16 scratch bits are associated with each MIR.
Memory Error Registers
Since errors recorded in the NERR regs are not signaled through the ERR[2:0]# or
MCERR# pins, FERR masking strategy should consider loss of external signaling on
subsequent error (NERR).
ECC errors are defined on a 32 byte ECC word. Since there are two words in each cache
line, an error can occur in both halves of the cache line. This can result in both FERR
and NERR registers being populated. If an address bus error occurs, this will normally
corrupt ECC in both halves of the cache line.
Normally, if a M1Err is indicated another uncorrectable error bit is set to indicate what
type of transaction (scrub, sparing) generated the error.
Device:
Function:
Offset:
Device:
Function:
Offset:
15:4
15:0
if MIR[i].LIMIT[11:0] > MIR[i-1].LIMIT[11:0]
3:2
Bit
Bit
1
0
if MIR[i].LIMIT[11:0] > TOLM > MIR[i-
if MIR[i].LIMIT[11:0] <= TOLM
Limit with Respect to TOLM
®
Attr
Attr
RW
RW
RW
RW
RV
5100 MCH Chipset
16
1
84h, 80h
16
1
90h, 8Ch
1].LIMIT[11:0]
>= TOLM
Default
Default
0000h
000h
00
0
0
LIMIT: This field defines the highest address in the range A[38:28] prior to
modification by the TOLM register.
Note:
Reserved
WAY1: Channel 1 participates in this MIR range if : this bit is set AND (the
way-sensitive address bit is 1b OR WAY0 of this MIR is 0b).
WAY0: Channel 0 participates in this MIR range if : this bit is set AND (the
way-sensitive address bit is 0b OR WAY1 of this MIR is 0b).
ADJLIMIT: Adjusted MIR Limit
The maximum value is 400h (512 GB), and the minimum value is 1h
(256 MB). The most-significant bit of this field is ignored.
then MIR[i].LIMIT[11:0] + (10H - TOLM) > A[38:28] >=
then MIR[i].LIMIT[11:0] + (10H - TOLM) > A[38:28] >=
then MIR[i].LIMIT[11:0] > A[38:28] >= MIR[i-
MIR[i-1]
Description
Description
Intel
MIR[i-1]
1
.LIMIT[11:0] + (10H - TOLM)
®
1]
Match MIR[i]
5100 Memory Controller Hub Chipset
1
.LIMIT[11:0]
1
.LIMIT[11:0]
Datasheet
199