HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 225

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
July 2009
Order Number: 318378-005US
Device:
Function:
Offset:
31:6
3:2
Bit
5
4
1
0
®
Attr
RW
RW
RW
RW
RW
RV
5100 MCH Chipset
8
0
48h
Default
0h
0h
0h
0
0
1
Reserved.
DMA_OO_MMIO_FETCH_CMP_ENABLE: DMA Out of Order Fetch
completion enable for MMIO writes
This field controls the enforcement of a weak/strongly ordered model for
pushing MMIO writes to the destination NIC. The weakly ordered model allows
for writes to be completed out of order with increased performance since the
DMA does not have to wait for the completions (in linear order) from the CE
and the overall throughput is higher.
0: Disable out-of-order write fetches and enforce serialization of write
requests to the destination (default).
1: Enable DMA Engine to complete out-of-order write fetches to the
destination (MMIO) for maximizing performance.
It is the responsibility of the BIOS/Software to program this register field
appropriately based on the usage/Producer-consumer requirements.
Note:
Note:
DMA_CONC_FETCH_DISABLE_: DMA Concurrent Fetch Disable
This field provides defeature control for enabling/disabling the concurrent
fetch request optimization to maximize data throughput of the DMA Engine.
0: Enable concurrent fetch and data transfer (i.e., overlapped read/write
during fetch phase) for performance (default)
1: Disable concurrent fetch operation, i.e., Read and Write fetch requests will
be serialized.
NUM_DMA_PREF: Number of outstanding DMA Prefetches
This field controls the total number of DMA prefetches that are outstanding for
both reads and writes issued by the DMA Engine across all four channels
00: 24 (12 Reads + 12 writes) (default)
01: 20 (10 Reads + 10 writes)
10: 16 (8 Reads + 8 writes)
11: Reserved
The default value is to enable the DMA Engine to prefetch up to 24 Cache lines
(Reads and writes) for maximum performance. For system debug or for any
issues leading to starvation of transaction IDs or bandwidth problems, this
register field can be manipulated to reduce the DMA Engine’s prefetch limit.
MSICBEN: MSI DMA Engine Interrupt Enable
1: Enables MSI messages (errors or Channel completions) to be sent to the
root complex for DMA Engine interrupts on the DMA Engine
0: Disables sending of MSI messages for DMA Engine Interrupts to the root
complex.
Note that for MSI DMA Engine DMA interrupt messages to be sent, both
MSICBEN and MSICTRL.MSIEN bits defined in
DMAEN: DMA Enable
1: Enables DMA Engine to perform DMA Engine related data transfers (M2M or
M2MMIO)
0: Disables DMA Engine from performing DMA Engine related data transfers
(M2M or M2MMIO). Read accesses to CB_BAR MMIO space (up to 300h in
Device 8, function 1) will return 0’s and writes will have no effect.
The DMAEN is a feature bit that controls DMA transfers for all the supported
channels of the DMA Engine and must be enabled for normal operation.
In either mode setting, all writes are completed before a status write
or interrupt is generated and then the next descriptor (if any) is read
from memory by the DMA Engine for further processing.
In the case of memory to memory transfers, the Intel
Chipset CE acks the fetch completion immediately (when there is no
conflict) and since the DMA Engine issues fetches in order, the fetch
completions also follow suit and are therefore amenable for pipelining
without any reordering penalty for the general case.
1
Description
Intel
®
5100 Memory Controller Hub Chipset
Section 3.8.10.3
®
have to be set.
5100 MCH
Datasheet
225