HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 300

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Figure 21.
Intel
Datasheet
300
®
5100 Memory Controller Hub Chipset
PCI Hot Plug* Interrupt Flow
4. PCI Hot Plug* - Chipset will receive an Assert/Deassert GPE message from the PCI
5. PCI Express* Power management - PCI Express* sends a PME message. Chipset
Express* port when a PCI Hot Plug* event is happening. Assert/Deassert GPE
messages should be treated the same as Assert/Deassert GPE messages for PCI
Hot Plug*. (Keep track of Assert/Deassert GPE messages from each port and send
Assert_GPE, Deassert_GPE message to ESI appropriately)
sends Assert_PMEGPE to ESI port when a power management event is detected.
a.
HPGPEEN
Upon receipt of the PME message, the Intel
PEXRTSTS.PMESTATUS bit corresponding to that port and send Assert_PMEGPE
to ESI port to generate the interrupt. (Assert_PMEGPE should be sent if one or
more of the PMESTATUS bits are set and enabled.) To generate an SCI (ACPI),
1
0
0
0
0
(PEXCTRL.HPGPE EN
(PEXSLOTCTRL[x].
(PEXCMD[x].INTx
HPINTEN == 1)
Disable == 1)
(MSICTRL[x].
MSIEN == 1)
PEXHPINT
== 1)
N
Y
N
Y
HPINTEN
x
1
1
1
0
Y
Y
N
N
Sends Assert_INTx
message via ESI
Intel® 5100 MCH Chipset
Sends MSI per MSIAR
And MSIDR
per INTP
Intel® 5100 MCH Chipset
Intel® 5100 MCH Chipset
Sends Assert_HPGPE
message via ESI
SW polls
MSIEN
status
x
1
0
0
x
Intel
®
5100 MCH Chipset—Functional Description
®
5100 MCH Chipset will set the
INTx Disable
Intel® 5100 MCH Chipset
cleared (wired-OR)
Sends Deassert_HPGPE
respective bits
PEXSLOTSTS are
message via
ESI when the
Intel® 5100 MCH Chipset
Sends Deassert_INTx
0
1
x
x
x
respective bits of
PEXSLOTSTS are
message via ESI
cleared (wired-
OR)
Order Number: 318378-005US
when the
Assert_HPGPE
Assert_INTx
Output
MSI
0117081802
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July 2009