HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 28

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 1.
Intel
Datasheet
28
®
5100 Memory Controller Hub Chipset
Terminology (Sheet 6 of 6)
SDDC
SDR
SDRAM
SEC/DED
Secondary PCI
Serial Presence
Detect (SPD)
Simplex
Single-Sided
DIMM
SMBus
Snooping
Split Lock
Sequence
Split Transaction
SSTL
SSTL_18
SSTL_2
Sticky Bits
Symbol
Symbol Time
System Bus
Target
Tenured
Transaction
TID
Transaction, Txn
Transmitter
Upstream
Terminology
Single Device Disable Code; aka x4 or x8 chip-disable Hamming code to protect single
DRAM device (x4 or x8 data width) failure.
Single Data Rate SDRAM.
Synchronous Dynamic Random Access Memory.
Single-bit Error Correct/Double-symbol Error Detect
The physical PCI interface driven directly by the MCH. It supports a subset of 32-bit, 66
MHz PCI 2.0 compliant components, but only at 1.5 V (not 3.3 V or 5 V).
A two-signal serial bus used to read and write Control registers in the SDRAM’s via the
SMBus protocol
A connection or channel that allows data or messages to be transmitted in one direction
only.
Terminology often used to describe a DIMM that contains one DRAM row. Usually one row
fits on a single side of the DIMM allowing the backside to be empty.
System Management Bus. Mastered by a system management controller to read and write
configuration registers. Signaling and protocol are loosely based on the I
limited to 100 kHz.
A means of ensuring cache coherency by monitoring all coherent accesses on a common
multi-drop bus to determine if an access is to information resident within a cache. The
Intel
with the address of any line that might appear in a cache on that bus.
A sequence of transactions that occurs when the target of a lock operation is split across a
processor bus data alignment or Cache Line boundary, resulting in two read transactions
and two write transactions to accomplish a read-modify-write operation.
A transaction that consists of distinct Request and Completion phases or packets that
allow use of bus, or interconnect, by other transactions while the Target is servicing the
Request.
Stub-Series Terminated Logic
Stub Series Terminated Logic for 1.8 V (DDR2)
Stub Series Terminated Logic for 2.6 V (DDR)
Register bits, whose value remains unchanged when system is RESET
An expanded and encoded representation of a data Byte in an encoded system (for
example, the 10-bit value in a 8-bit/10-bit encoding scheme). This is the value that is
transmitted over the physical medium.
The amount of time required to transmit a symbol.
Processor-to-Intel
to operation at 266/533/1066, 333/667/1333 (Bus Clock/Address/Data). The system bus
is not compatible with the P6 system bus.
A device that responds to bus Transactions. The agent receiving a request packet is
referred to as the Target for that Transaction.
A transaction that holds the bus, or interconnect, until complete, effectively blocking all
other transactions while the Target is servicing the Request.
Transaction Identifier; A multi-bit field used to uniquely identify a transaction. Commonly
used to relate a Completion with its originating Request in a Split Transaction system.
An overloaded term that represents an operation between two or more agents that can be
comprised of multiple phases, cycles, or packets.
1.
2.
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound”
®
5100 MCH Chipset ensures coherency by initiating snoops on the processor busses
The Agent that sends a Packet across an interface regardless of whether it was
the original generator of the packet.
More narrowly, the circuitry required to drive signals onto the physical medium.
®
5100 MCH Chipset interface. The system bus in this document refers
Description
Intel
®
5100 MCH Chipset—Introduction
Order Number: 318378-005US
2
C* Interface,
July 2009