HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 252

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.12.0.3
3.12.0.4
3.12.0.5
3.12.0.6
Intel
Datasheet
252
®
5100 Memory Controller Hub Chipset
PPRSETLEN[3:2] - Per-Port Register Set Length Register
STRMPRI[3:2]: Stream Priority Register
REQID[3:2] - Requestor ID Register
The Requester ID register is programmed such that the chipset can differentiate
between devices which implement prioritized streams and those which do not. Since
the MCH does not support stream priority, this register is RO.
STRMCAP[3:2] - Stream Capacity Register
This register defines the chipset’s capacity to implement an arbitrary number of
streams for DMA Engine. The MCH will implement and support 2 streams each for ports
2 and 3.
Offset:
Offset:
7:4
3:0
Offset:
15:8
7:3
2:0
7:0
Bit
Bit
Bit
RO
RW
RO
RO
RO
Attr
Attr
Attr
RO
382h, 302h
383h, 303h
384h, 304h
0000
0000
0h
0h
0h
Default
Default
Default
60h
PPRSLEN: PPR Set Length
This register indicates the length of the per-port register set in bytes (including
NXTPPRSET, and PPRSETLEN).
Highest_pri_supported: Highest Priority Supported
The Intel
is initialized to 0.
Def_strmpri: Default Stream Priority
This field specifies the priority given to StreamIDs greater than the number of
streams supported.
If a stream priority greater than 0 is set in this register field, the Intel
Chipset will treat the stream priority for the exceeding streams to default to that of
priority 0.
BN: Bus Number
This field indicates the bus number which the device implementing streams resides
on. This is reflected in the Requester ID field of the PCI Express* packet. The
chipset checks this register against the incoming transaction’s header before
applying stream prioritization.
DN: Device Number
This field indicates the device number which the device implementing streams
resides on. This is reflected in the Requester ID field of the PCI Express* packet.
The chipset checks this register against the incoming transaction’s header before
applying stream prioritization.
FN: Function Number
This field indicates the function number which the device implementing streams
resides on. This is reflected in the Requester ID field of the PCI Express* packet.
The chipset checks this register against the incoming transaction’s header before
applying stream prioritization.
®
5100 MCH Chipset does not support stream priority and hence this field
Intel
Description
Description
Description
®
5100 MCH Chipset—Register Description
Order Number: 318378-005US
®
5100 MCH
July 2009