HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 305

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Figure 23.
5.11
5.12
July 2009
Order Number: 318378-005US
No Interrupt Swizzle
For additional information, please refer to document number 314337, Interrupt
Swizzling Solution for Intel
available on http://www.intel.com/.
Interrupt Error Handling
Software must configure the system so that each interrupt has a valid recipient. In the
event that an interrupt doesn’t have a valid recipient, since the Intel
Chipset will not necessarily know that the interrupt is targeted for a non-existing
processor, will deliver the interrupt to the processor buses following the interrupt
routing rules described in this section. If the interrupt targets a non-existing processor,
it may be ignored but the transaction should still complete.
Any error in the data part of an interrupt message, interrupt acknowledge, or EOI will
be treated the same way as data error with any other transaction – single bit errors will
be corrected by ECC, double bit error will be treated and logged as uncorrectable. For
more details on error handling, please refer to
Enterprise South Bridge Interface (ESI)
The Enterprise South Bridge Interface (ESI) in the Intel
to-chip connection to the ICH9R see
Chipset to ICH9R Enterprise South Bridge Interface.”
standard PCI Express* Base Specification, Rev. 1.0a with special commands/features
added to enhance the PCI Express* interface for enterprise applications. This high-
speed interface integrates advanced priority-based servicing allowing for concurrent
traffic transfer capabilities. Base functionality is completely transparent permitting
current and legacy software to operate normally. For the purposes of this document,
the ICH9R will be used as a reference point for the ESI discussion in the Intel
MCH Chipset.
®
5100 MCH Chipset
®
5000 Chipset Series-based Platforms – Application Note
Figure 24, “Intel® 5100 Memory Controller Hub
Section 5.2.4, “Memory
Intel
The ESI is an extension of the
®
®
5100 MCH Chipset is the chip-
5100 Memory Controller Hub Chipset
®
5100 MCH
RAS”.
®
Datasheet
5100
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