HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 287

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.2.7
5.2.7.1
5.2.7.2
5.2.7.3
5.2.7.4
5.2.7.5
5.2.8
5.2.8.1
July 2009
Order Number: 318378-005US
signals are equally utilized for data and the ECC code layout. The same mapping of
symbols to data and code bits applies to Northbound and Southbound data for each of
the two independent DDR2 memory channels of the MCH.
The Intel
as 32-byte aligned cache line accesses. In 32-byte aligned accesses, data is returned
critical word first; the MCH returns the addressed cache line but with the two halves
reversed in time order so that the “addressed” half cache line arrives first – the
addressed half cache line is referred to as the “critical” word or half of the cache line.
DDR2 Protocol
Posted CAS
Posted CAS timing is used. RAS to CAS delay will be 3 cycles in all cases.
Refresh
Regardless of the number of DIMMs installed, each rank will get a minimum of one
refresh every eight periods defined by the DRTA.TREF configuration register field. The
refreshes cycle through all eight DIMM ranks.
Access Size
All memory accesses are 64 bytes in size, issued with a burst length of 8.
Transfer Mode
Each DIMM is programmed to use a burst-length of 64 bytes (eight transfers) across
the channel. The Mode Register of each DIMM must be programmed for a burst length
of eight, and interleave mode.
Invalid and Unsupported DDR Transactions
The memory controller prevents cycle combinations leading to data interruption or
early termination. The memory controller prevents combinations of DDR commands
that create bus contention (i.e., where multiple ranks would be required to drive data
simultaneously on a DIMM). The memory controller does not interrupt writes for reads.
A precharge command is provided, but early read or write termination due to precharge
is not supported.
Memory Thermal Management
The Intel
with electrical throttling to limit the number of memory requests to the DIMMs. The
methodology is comprised of the following:
Closed Loop Thermal Activate Throttle Control
Since there is no means to obtain the DIMM temperatures, Closed Loop Thermal
Throttling is not supported.
1. Activation throttling: Consists of open loop throttling of activations on the DDR2
2. Electrical throttling is used to prevent silent data corruption by limiting the number
interface. Open Loop Global Activation Control limits requests when the number of
activations crosses an event threshold in a large time window.
of activations per rank within a short sliding window period.
®
®
®
5100 MCH Chipset supports cache line or 64-byte aligned accesses as well
5100 MCH Chipset implements an adaptive throttling methodology along
5100 MCH Chipset
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
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