HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 22

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

1.0
Note:
1.1
Intel
Datasheet
22
®
5100 Memory Controller Hub Chipset
Introduction
The Intel
code-named San Clemente or SC) is designed for systems based on the Dual-Core
Intel
Dual-Core Intel
5400 series, and Intel
1066 MT/s and 1333 MT/s. The Intel
main components: the Memory Controller Hub (MCH) for the host bridge and the I/O
Controller Hub (ICH) for the I/O subsystem. The Intel
platform uses the Intel
The Intel
a 1432 pin FCBGA package with integrated heat spreader. The balls are on 1.092 mm
(43 mil) centers. The overall package dimensions are 42.5 mm by 42.5 mm.
The Intel
supports a 771-land, FC-LGA4 (Flip Chip Land Grid Array 4) package for the Quad-Core
and Dual-Core Intel
matching LGA771 socket. The surface mount, LGA771 socket supports Direct Socket
Loading (DSL).
The Intel
supports 479-ball Micro-FCBGA (Flip Chip Ball Grid Array) and 478-pin Micro-FCPGA
(Flip Chip Pin Grid Array) packages for the Intel
The Dual-Core Intel
processor 5300 series return a processor signature of 06Fxh, and the Dual-Core Intel
Xeon
Intel
CPUID instruction is executed with EAX=1. The x represents the stepping number.
Refer to the appropriate processor Specification Update for more information on
processor signature.
Unless otherwise specified, the term “processor” in this document refers to the Dual-
Core Intel
series, Dual-Core Intel
processor 5400 series, and Intel
specified, the term “MCH” in this document refers to the Intel
Terminology
This section provides the definitions of some of the terms used in this document.
®
®
®
Xeon
Core™2 Duo Processor T9400 return a processor signature of 1067xh, when the
processor 5200 series, Quad-Core Intel
®
®
®
®
®
5100 MCH Chipset is implemented in a 0.13 µm silicon process, packaged in
5100 Memory Controller Hub Chipset (Intel
5100 MCH Chipset-based platform for Dual-Processor (DP) system designs
5100 MCH Chipset-based platform for Uni-Processor (UP) system designs
®
Xeon
processor 5100 series, Quad-Core Intel
®
®
Xeon
processor 5100 series, Quad-Core Intel
®
®
®
Xeon
Xeon
®
®
®
Core™2 Duo Processor T9400 and supports FSB operation of
processor 5200 series, Quad-Core Intel
Xeon
82801IR I/O Controller Hub (ICH9R).
®
®
Processor 5000 Sequence. This package uses the
processor 5100 series and Quad-Core Intel
®
processor 5200 series, Quad-Core Intel
®
Core™2 Duo Processor T9400. Unless otherwise
®
5100 MCH Chipset-based platforms contain two
®
®
Xeon
Core™2 Duo Processor T9400.
Intel
®
®
®
®
Xeon
5100 MCH Chipset-based
processor 5400 series and
5100 MCH Chipset, formerly
®
®
5100 MCH Chipset—Introduction
®
Xeon
®
processor 5300 series,
Order Number: 318378-005US
5100 MCH Chipset.
®
®
Xeon
processor 5300
®
®
®
processor
Xeon
Xeon
®
®
July 2009
®