HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 54

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

2.7
Table 21.
Intel
Datasheet
54
®
5100 Memory Controller Hub Chipset
Clocks, Reset and Miscellaneous
Clocks, Reset and Miscellaneous Signals (Sheet 1 of 2)
48GB_Mode
ASYNCRFSH
CORECLKN
CORECLKP
ERR[2:0]#
FSBCRES
FSBODTCRES
FSBSLWCRES
FSBSLWCTRL
Signal Name
Analog
Analog
Analog
Analog
Analog
Power/
Other
Type
O
I
I
48 GB DDR2 Memory Mode Selection:
This pin is a strap pin to control whether 48 GB maximum (48 GB mode) or 32
GB maximum (32 GB mode) memory support is enabled. By strapping this pin
High, 6 ranks are supported per DDR channel, enabling 48 GB memory
support.
By strapping this pin Low, four ranks are supported per DDR channel, enabling
32 GB memory support. This mode provides backward compatibility for
boards designed for A0 versions of silicon limited to 32 GB of memory.
The strapping of the 48GB_Mode pin affects the function of the following
signals CH0_A[15], CH0_CKE[3], CH0_DCLKN[3], CH0_DCLKP[3],
CH1_A[15], CH1_CKE[3], CH1_DCLKN[3], and CH1_DCLKP[3]. See the Quad-
Core and Dual-Core Intel
Memory Controller Hub Chipset for Communications, Embedded, and Storage
Applications – Platform Design Guide or Intel
and SL9400 and Intel
Communications and Embedded Applications – Platform Design Guide for
connection restrictions.
Note:
Asynchronous Request for Self-refresh:
Allows an asynchronous request to force DIMMs into Self-Refresh.
Differential Processor Core Clock Negative Phase:
These pins receive a low-voltage differential host clock from the external clock
synthesizer. This clock is used by all of the MCH logic that is in the Host clock
domain.
Differential Processor Core Clock Positive Phase:
These pins receive a low-voltage differential host clock from the external clock
synthesizer. This clock is used by all of the MCH logic that is in the Host clock
domain.
Error Output:
Error output signal recommended configuration:
ERR[0] = Correctable and recoverable error from the memory subsystem
ERR[1] = Uncorrectable error from the Intel
ERR[2] = Fatal error from the Intel
Note: The error assignments to the ERR[2:0] pins are configurable with the
use of the
Register”. These signals are Open Drain (OD) outputs; see the Quad-Core and
Dual-Core Intel
Controller Hub Chipset for Communications, Embedded, and Storage
Applications – Platform Design Guide or Intel
and SL9400 and Intel
Communications and Embedded Applications – Platform Design Guide for pull-
up requirements.
Processor Bus Compensation:
Processor Bus Compensation:
Processor Bus Slew Rate Compensation:
Processor Bus Slew Rate Control:
The 48 GB mode is the recommended mode of operation for current
designs.
, “PEX_ERR_DOCMD[7:2,0] - PCI Express* Error Do Command
®
Xeon
®
®
®
5100 Memory Controller Hub Chipset for
5100 Memory Controller Hub Chipset for
®
Processor 5000 Sequence with Intel
Xeon
Intel
®
Description
®
Processor 5000 Sequence with Intel
®
5100 MCH Chipset—Signal Description
5100 MCH Chipset
®
®
®
5100 MCH Chipset
Core™2 Duo Processors T9400
Core™2 Duo Processors T9400
Order Number: 318378-005US
®
5100 Memory
July 2009
®
5100