HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 340

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.17.5.2
5.17.5.2.1
5.17.5.3
Table 108.
5.17.5.3.1
Intel
Datasheet
340
®
5100 Memory Controller Hub Chipset
The above rules apply whether the transaction is coherent or non-coherent. Some
regions of memory space are considered non-coherent (Don’t Snoop attribute is set).
The MCH PCI Express* cluster will order all transactions regardless of its destination.
Outbound Transaction Ordering Rules
Outbound transactions through the MCH are memory, I/O, or configuration read/write
transactions originating on a processor interface destined for a PCI Express* device.
Multiple transactions destined for the same PCI Express* port are ordered according to
the ordering rules specified in PCI Express* Base Specification, Rev. 1.0a.
Outbound Ordering Requirements
There are no ordering requirements between outbound transactions targeting different
PCI Express* interfaces. For deadlock avoidance, the following rules must be ensured
for outbound transactions within the same PCI Express* interface:
RULE 1: Inbound non-posted completions must be allowed to progress past stalled
RULE 2: Outbound posted write requests must be allowed to progress past stalled
RULE 3: Outbound non-posted requests, outbound messages, outbound write
The Producer - Consumer model prevents read requests, write requests, and read
completions from passing write requests. Refer to PCI Local Bus Specification, Rev. 2.3
for details on the Producer - Consumer ordering model.
RULE 4: Posted outbound messages must follow the same ordering rules as outbound
RULE 5: If a non-posted inbound request requires multiple sub-completions, then
MCH Ordering Implementation
Table 108
port by the MCH.
MCH Ordering Implementation
Peer-to-peer Ordering
All peer-to-peer memory write transactions are treated as non-coherent memory writes
by the system. Peer-to-peer memory reads are treated as non-coherent reads.
On the MCH, any peer-to-peer transaction is ordered with other inbound transactions
from the same PCI Express* port. This provides a serialization point for proper ordering
(e.g., cases where the flag and data are not in the same memory).
Posted requests
Non-Posted
Requests
Completions
Transaction
outbound non-posted requests.
outbound non-posted requests.
requests, and inbound completions cannot pass enqueued outbound posted
write requests.
posted writes.
those sub-completions must be delivered in linearly increasing address order.
summarizes the rules enforced on transactions from a given PCI Express*
Will the transaction
Posted Request?
pass a stalled
never
never
never
Will the transaction pass a stalled Non-
architectural ordering requirement is
Can happen in implementation; no
Posted Request?
Intel
imposed
always
always
®
5100 MCH Chipset—Functional Description
Order Number: 318378-005US
Will the transaction
pass a stalled
completion?
always
always
never
July 2009