HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 285

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
5.2.5
Figure 19.
July 2009
Order Number: 318378-005US
Refer to
DIMM Memory Configuration Mechanism
Before any cycles to the memory interface can be supported, the Intel
Chipset DRAM registers must be initialized. The MCH must be configured for operation
with the installed memory types. Detection of memory type and size is accomplished
via the Serial Presence Detect (SMBus) interface on the MCH. The SMBus interface is a
two-wire bus used to extract the DRAM type and size information from the Serial
Presence Detect port on the DIMMs.
The DIMMs contain a 6-pin Serial Presence Detect interface, which includes SCL (serial
clock), SDA (serial data), and SA[2:0] (serial address). Devices on the SMBus bus have
a 7-bit address. For the DIMMs, the upper four bits are fixed at 1010. The lower three
bits are strapped via the SA[2:0] pins. SCL and SDA are connected to the respective
SPD0SMBDATA, SPD0SMBCLK pins on the MCH, see
Serial I/O Signals.”
The Intel
SPD EEPROM’s. There is one SPD port. SPD0SMBDATA, and SPD0SMBCLK are defined
for channel 0 and channel 1. There can be a maximum of eight SPD EEPROM’s
associated with an SPD bus. Therefore, the SPD interface is wired as indicated in
Figure 19, “Connection of DIMM Serial I/O Signals.”
Connection of DIMM Serial I/O Signals
Board layout must map chip selects to SPD Slave Addresses as shown in
Addressing.”
Section 3.9.11.2, “SPDCMD: Serial Presence Detect Command
on the use of SA[2:0] in generating an SPD bus address related to DIMM EPROM access
see
Section 5.20.6, “DDR2 DIMM SPD0 SMBus
Section 5.2.6.1, “Inbound ECC Code Layout for Memory Interface”
®
®
5100 MCH Chipset integrates a 100 kHz SPD controller to access the DIMM
5100 MCH Chipset
The slave address is written to the SPDCMD configuration register (see
Intel® 5100 Memory
Controller Hub
Chipset
SPD0SMBDATA
SPD0SMBCLK
Channel 0
Channel 1
Interface”.
Figure 19, “Connection of DIMM
Intel
®
5100 Memory Controller Hub Chipset
Register”). For details
0814061820
®
Table 90, “SPD
5100 MCH
for details.
Datasheet
285