HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 157

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.12
3.8.12.1
3.8.12.2
July 2009
Order Number: 318378-005US
PCI Express* Advanced Error Reporting Capability
PEXENHCAP[7:2,0] - PCI Express* Enhanced Capability Header
This register identifies the capability structure and points to the next structure.
UNCERRSTS[7:2] - Uncorrectable Error Status
This register identifies uncorrectable errors detected for the PCI Express* Port. If an
error occurs and is unmasked in the detect register (EMSAK_UNCOR_PEX), the
appropriate error bit will be recorded in this register. If an error is recorded in the
UNCERRSTS register and the appropriate bit (along with the severity bit of the
UNCERRSEV register) determines which bit in the PEX_FAT_FERR, PEX_NF_COR_FERR,
PEX_FAT_NERR, PEX_NF_COR_NERR register gets recorded. These error log registers
are described starting from
First Fatal Error Register.”
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
31:20
19:16
31:21
15:0
3:0
Bit
Bit
Bit
20
19
18
®
Attr
Attr
RW
RO
RO
RO
RWCST
RWCST
5100 MCH Chipset
Attr
0
0
D4h
7-2, 0
0
100h
2-3, 4-7
0
104h
RV
RV
Default
Default
0001h
000h
0h
1h
Default
0h
0
0
0
SAC: STOPGRANT ACK COUNT
This field tracks the number of Stop Grant Acks received from the FSBs. The
MCH will forward the last StopGrantAck received from the FSB to the ICH9R
using the “Req_C2” command. Software is expected to set this field to
“THREADs-1” where the variable “THREAD” is the total number of logical
threads present in the system (currently can handle up to 16). Typically each
CPU thread will issue a StopGrantAck in response to a STPCLK# assertion from
the ICH9R. When the final StopGrantAck is received from the FSB and the
internal counter hits the value of SAC+1 (which is equal to THREAD), the MCH
will initiate the “Req_C2” command on the ESI.
It is illegal for the CPU to send more Stop Grant Acks than that specified in the
“THREAD” variable.
Note:
NCAPOFF: Next Capability Offset
This field points to the next Capability in extended configuration space.
CV: Capability Version
Set to 1h for this version of the PCI Express* logic
PEXCAPID: PCI Express* Extended CAP_ID
Assigned for advanced error reporting
Section 3.8.12.24, “PEX_FAT_FERR[7:2,0] - PCI Express*
Reserved
IO2Err: Received an Unsupported Request
Reserved
IO9Err: Malformed TLP Status
For Sx Power management in H/W or S/W mode
Description
Description
Intel
Description
®
5100 Memory Controller Hub Chipset
Datasheet
157