HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 95

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.1.3.1
3.8.1.3.2
Figure 11.
3.8.1.4
July 2009
Order Number: 318378-005US
Stepping Revision ID (SRID)
The SRID is a 4-bit hardwired value assigned by Intel, based on product’s stepping. The
SRID is not a directly addressable PCI register. The SRID value is reflected through the
RID register when appropriately addressed. The 4 bits of the SRID are reflected as the
two least significant bits of the major and minor revision field respectively. See
Figure 11, “Intel® 5100 Memory Controller Hub Chipset Implementation of SRID and
CRID Registers.”
Compatible Revision ID (CRID)
The CRID is an 4-bit hardwired value assigned by Intel during manufacturing process.
Normally, the value assigned as the CRID will be identical to the SRID value of a
previous stepping of the product with which the new product is deemed “compatible”.
The CRID is not a directly addressable PCI register. The CRID value is reflected through
the RID register when appropriately addressed. The 4 bits of the CRID are reflected as
the two least significant bits of the major and minor revision field respectively. See
Figure 11, “Intel® 5100 Memory Controller Hub Chipset Implementation of SRID and
CRID Registers.”
Intel
CRID Registers
CCR - Class Code Register
This register contains the Class Code for the device. Writes to this register have no
effect.
Device
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
23:16
15:8
Bit
®
1
:
Attr
5100 Memory Controller Hub Chipset Implementation of SRID and
RO
RO
®
5100 MCH Chipset
0, 2-7
0
09h
16
0, 1, 2
09h
21, 22
0
09h
(DEV2-7)
Default
{04h}
{00h}
06h
else
if
Base Class.
This field indicates the general device category. For the MCH, this field is hardwired
to 06h, indicating it is a “Bridge Device”.
Sub-Class.
This field qualifies the Base Class, providing a more detailed specification of the
device function.
For PCI Express* Devices 2, 3, 4, 5, 6, 7 default is 04h, indicating “PCI-to-PCI
Bridge”
For all other Devices: 0, 16, 19, 21, 22 default is 00h, indicating “Host Bridge”. See
footnote 1, for DMA Engine device CCR.
Major Rev Id Minor Rev Id
7
6
5
4
3
Description
2
Intel
1
®
0
5100 Memory Controller Hub Chipset
Datasheet
95