HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 322

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

5.14.2
5.14.2.1
Caution:
5.14.3
Intel
Datasheet
322
®
5100 Memory Controller Hub Chipset
Basic Approaches
Software Model - Assistance from OS-level Software
The DMA Engine device is an I/O device (i.e., PCI base class and subclass do not
indicate a host bridge). The system BIOS is not required to provide special support for
DMA Engine and DMA Engine register address space requirement is reported in the PCI
configuration header. There is a DMA Engine device driver that loads under the host
operating system. This driver assists in performing required startup/tear-down steps
and can optionally also provide a measure of abstraction/de-coupling between the
client I/O device and DMA Engine. For example, the DMA Engine driver is responsible
for detecting the version, capabilities, and limitations of the current DMA Engine
implementation, so that the client can get that information from the DMA Engine device
driver. In addition, the DMA Engine device driver provides programming interfaces to
reserve and release DMA Engine resources (e.g., DMA channels). Optionally, the DMA
Engine driver could provide an abstracted programming interface to use all DMA Engine
capabilities (e.g., to program DMA operations) so that the client does not have to be
aware of the DMA Engine register layout and register formats in order to use it. Another
possible usage model is one in which the host based client uses the DMA Engine driver
for startup/tear-down operations but the client directly uses DMA Engine resources
(e.g., DMA channel) at run time once its device driver has reserved it. In this model:
Note that some variations in the basic usage models are possible. For example, the OS
based device driver for the client I/O device can also act as the DMA Engine device
driver or otherwise assist clients with DMA Engine hardware.
It is very difficult to support a model in which some client I/O devices want to use DMA
Engine with OS level software assistance while other client I/O devices want to do so
without any OS level software assistance. The current version of DMA Engine does not
provide any additional capabilities to support such a hybrid model.
A client may want to use DMA Engine features in the pre-boot environment. This can be
accomplished in multiple platform specific ways. For example, the platform BIOS could
contain DMA Engine specific code similar to an operating system based DMA Engine
driver. However, there are no standard interfaces (e.g., INT XX calls) to invoke such
DMA Engine specific software in the pre-boot environment, so the client would need to
take platform specific steps to invoke it. Another possibility is that the option ROM of
the client I/O device could contain DMA Engine specific code to manage DMA Engine.
Power Management Considerations
Chipset devices that implement DMA Engine technology as well as clients that use DMA
Engine may support different device power states. At a minimum, all devices in the
system must support a D0 device power state that corresponds to the “fully-on” state
and a D3 device power state that corresponds to the “fully-off” state. Intermediate
device power states D1 and D2 may or may not be supported. Thus, there can be
multiple permutations with DMA Engine and/or its client I/O devices supporting the
same or different device power states. Care must be taken to ensure that a power
management capable operating system does not put the DMA Engine device to a lower
device power (D1, D2 or D3) state while its client I/O device is fully powered on (D0
1. The DMA Engine device driver must provide the clients a mechanism (programming
2. The client must be able to communicate with the DMA Engine device driver to use
interface) to detect DMA Engine version and capabilities. It must also provide
clients a mechanism to reserve and release DMA Engine resources. Optionally, it
may provide an abstracted mechanism to use/program DMA Engine capabilities, if
this is desired.
its services to reserve and release DMA Engine resources.
Intel
®
5100 MCH Chipset—Functional Description
Order Number: 318378-005US
July 2009