HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 274

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Table 85.
1. SMM memory access control, see
2. Software must not cache this region.
3. One and only one BCTRL can set the VGAEN; otherwise, send to ESI.
4. Notice this range is mapped into legacy SMM range (A_0000h to B_FFFFh).
4.4.3
Table 86.
Intel
Datasheet
274
SMM region
Extended
SMRAM
(TSEG)
High SMM
®
5100 Memory Controller Hub Chipset
ESMMTOP -TSEG_SZ
to
ESMMTOP
FEDA_0000h
to
FEDB_FFFFh
Decoding Processor Requests to SMM and VGA Spaces (Sheet 2 of 2)
Inbound Transactions
In general, inbound I/O transactions are decoded and dispositioned similarly to
processor transactions. The key differences are in SMM space, memory mapped
configuration space, and interrupts. Inbound transaction targeting at itself will be
master aborted.
Note that inbound accesses to the SMM region must be handled in such a way that FSB
snooping and associated potential implicit writebacks are avoided. This is necessary to
prevent compromising SMM data by returning real content to the I/O subsystem. Note
also that DMA Engine is treated as an I/O device, thus accesses initiated by the DMA
Engine are considered as inbound accesses.
For all table entries where an access is forwarded to ESI to be master aborted, if an
access comes from ESI, the Intel
transaction without forwarding it back to the ESI.
Address Disposition for Inbound Transactions (Sheet 1 of 2)
Address Range
BIOS segments
Transaction
C, D, E, and F
Address
SMM/VGA
Range
DOS
Table 84, “SMM Memory Region Access Control from Processor.”
0 to 09FFFFh
0A0000h to 0BFFFFh and
VGAEN=0
0A0000h to 0BFFFFh and
VGAEN=1
0C0000h to 0FFFFFh and PAM=11
ESMMTOP -TSEG_SZ
to
ESMMTOP
A_0000h
to
B_FFFFh
SMM Memory
Address
Range
Conditions
®
5100 MCH Chipset ESI may master abort a
Control
x
x
yes
no
no
x
x
yes
no
no
Access
SMM
2
1
Coherent Request to Main Memory. Route to main
memory according to SC.MIR registers. Apply
Coherence Protocol.
Send to ESI to be master aborted. Set
EXSMRAMC.E_SMERR
Non-coherent read/write request to the decoded PCI
Express* or to ESI based on BCTRL
Non-coherent request to main memory. (Coherency
does not need to be guaranteed. Coherency protocol
can be followed if it simplifies implementation.) Route
to appropriate DDR2 DIMM according to SC.MIR
registers.
0
1
1
1
1
0
1
1
1
1
Intel
x
x
x
x
x
x
0
1
1
1
®
Intel
5100 MCH Chipset—System Address Map
x
0
1
1
1
x
x
x
x
x
®
5100 MCH Chipset Behavior
x
x
x
1
0
x
x
x
1
0
Order Number: 318378-005US
to identical system memory
by definition
to SMM memory
block access: master abort
set EXSMRAMC.E_SMERR
to ESI (where access will be
master aborted)
to SMM memory
block access: master abort
set EXSMRAMC.E_SMERR
Routing
1
4
July 2009