HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 178

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.13.11
3.8.13.12
3.8.13.13
Intel
Datasheet
178
®
5100 Memory Controller Hub Chipset
EMASK_FSB[1:0]: FSB Error Mask Register
A ‘0’ in any field enables that error.
ERR2_FSB[1:0]: FSB Error 2 Mask Register
This register enables the signaling of Err[2] when an error flag is set. Note that one and
only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
ERR1_FSB[1:0]: FSB Error 1 Mask Register
This register enables the signaling of Err[1] when an error flag is set. Note that one and
only one error signal should be enabled ERR2_FSB, ERR1_FSB, ERR0_FSB, and
MCERR_FSB for each of the corresponding bits.
Device:
Function:
Offset:
Device:
Function:
Offset:
Note:
Device:
Function:
Offset:
15:9
15:9
7:0
4:2
4:2
Bit
Bit
Bit
8
7
6
5
1
0
8
7
6
5
1
0
For systems without parity, the BIOS will have to write to this register to mask the parity error.
ROST
Attr
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
RWST
Attr
Attr
RV
RV
RV
RV
16
0
490h, 190h
16
0
492h, 192h
16
0
498h, 198h
Default
Default
Default
00h
0h
0h
0h
0h
1
1
1
1
1
1
1
1
1
1
1
1
A39DT32: FSB Address [39:32]
Reserved
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
Reserved
F9Msk: FSB Protocol Error
F8Msk: B-INIT
F7Msk: Detected MCERR
F6Msk: Data Parity Error
Reserved
F2Msk: Unsupported Processor Bus Transaction
F1Msk: Request/Address Parity Error
Intel
®
Description
5100 MCH Chipset—Register Description
Description
Description
Order Number: 318378-005US
July 2009