HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 104

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.3.11
3.8.3.12
3.8.4
3.8.4.1
Intel
Datasheet
104
®
5100 Memory Controller Hub Chipset
EXSMRAMC - Expansion System Management RAM Control Register
Other address mapping registers such as BCTRL (VGAEN), MBASE/LIMIT, PMBASE/
LIMIT, etc., are included with the PCI Express* registers described in this chapter.
HECBASE - PCI Express* Extended Configuration Base Address
Register
This register defines the base address of the enhanced PCI Express* configuration
memory.
Interrupt Redirection Registers
REDIRCTL - Redirection Control Register
This register controls the priority algorithm of the XTPR interrupt redirection
mechanism.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
15:12
31:24
23:12
11:0
6:0
Bit
Bit
Bit
7
RWC
Attr
Attr
RW
RV
RV
RV
Attr
RV
16
0
60h
16
0
64h
16
0
6Eh
Default
Default
001h
0h
0h
0h
0
Default
0h
E_SMERR: Invalid SMRAM Access
This bit is set when CPU has accessed the defined memory ranges in High SMM
Memory and Extended SMRAM (T-segment) while not in SMM space and with
the D-OPEN bit = 0. The MCH will set this bit if any In-Bound access from I/O
device targeting SMM range that gets routed to the ESI port (master abort).
Refer to
this bit when processor does a cache line eviction (EWB or IWB) to SMM
ranges regardless of SMMEM# on FSB.
It is software’s responsibility to clear this bit. The software must write a 1 to
this bit to clear it.
Reserved
Reserved
HECBASE: PCI Express* Extended Configuration Base
This register contains the address that corresponds to bits 39 to 28 of the base
address for PCI Express* extended configuration space. Configuration
software will read this register to determine where the 256 MB range of
addresses resides for this particular host bridge. This register defaults to the
same address as the default value for TOLM.
Reserved
Reserved
Section 4.4.3, “Inbound Transactions”
Intel
®
Description
Description
5100 MCH Chipset—Register Description
Description
for details. The MCH will not set
Order Number: 318378-005US
July 2009