HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 41

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Signal Description—Intel
Table 6.
July 2009
Order Number: 318378-005US
Processor Front Side Bus 1 Signals (Sheet 2 of 4)
FSB1BNR#
FSB1BPM[5:4]#
FSB1BPRI#
FSB1BREQ[1:0]#
FSB1D[63:0]#
Signal Name
®
5100 MCH Chipset
I/O
I/O
O
I/O
I/O
Type
Processor 1 Block Next Request:
FSB1BNR# is used to assert a bus stall by any bus agent who is unable to
accept new bus transactions. During a bus stall, the current bus owner cannot
issue any new transactions.
Since multiple agents might need to request a bus stall at the same time,
FSB1BNR# is a wired-OR signal which must connect the appropriate pins of all
processor FSB agents. In order to avoid wired-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, FSB1BNR# is
activated on specific clock edges and sampled on specific clock edges.
FSB1BNR# is used to block the current request bus owner from issuing a new
request. This signal is used to dynamically control the processor bus pipeline
depth.
Processor 1 Breakpoint Monitor/Debug Bus:
FSB1BPM[5:0]# are breakpoint and performance monitor signals. They are
outputs from the processor which indicate the status of breakpoints and
programmable counters used for monitoring processor performance.
FSB1BPM[5:0]# should connect the appropriate pins of all FSB agents.
FSB1BPM[4]# provides PRDY# (Probe Ready) functionality for the TAP port.
PRDY# is a processor output used by debug tools to determine processor debug
readiness.
FSB1BPM[5]# provides PREQ# (Probe Request) functionality for the TAP port.
PREQ# is used by debug tools to request debug operation of the processors.
FSB1BPM[5:4]# must be bussed to all bus agents. Please refer to the
appropriate platform design guidelines for more detailed information.
Processor 1 Priority Agent Bus Request:
FSB1BPRI# is used to arbitrate for ownership of the processor FSB. It must
connect the appropriate pins of all processor FSB agents. Observing FSB1BPRI#
active (as asserted by the priority agent) causes all other agents to stop issuing
new requests, unless such requests are part of an ongoing locked operation.
The priority agent keeps FSB1BPRI# asserted until all of its requests are
completed, then releases the bus by deasserting FSB1BPRI#.
The MCH is the only Priority Agent on the processor bus. It asserts this signal to
obtain ownership of the address bus. This signal has priority over symmetric
bus requests and cause the current symmetric owner to stop issuing new
transactions unless the FSB1LOCK# signal was asserted.
Processor 1 Bus Requests:
The MCH pulls the FSB1BREQ0# signal low during RESET#. The signal is
sampled by the processor on the active-to-inactive transition of FSB1RESET#.
Processor 1 Data Bus:
FSB1D[63:0]# are the data signals. These signals provide a 64-bit data path
between the processor FSB agents. The data driver asserts FSB1DRDY# to
indicate a valid data transfer.
FSB1D[63:0]# are quad-pumped signals, and will thus be driven four times in a
common clock period. FSB1D[63:0]# are latched off the falling edge of both
FSB1DSTBP[3:0]# and FSB1DSTBN[3:0]#. Each group of 16 data signals
correspond to one data strobe pair of FSB1DSTBP[3:0]# and
FSB1DSTBN[3:0]#. The below table shows the grouping of data signals to
strobes and FSB1DBI[3:0]#.
Furthermore, the FSB1DBI[3:0]# signals determine the polarity of the data
signals. Each group of 16 data signals corresponds to one of the
FSB1DBI[3:0]# signals. When a specific FSB1DBI[3:0]# signal is active, the
corresponding data group is inverted and therefore sampled active high.
FSB1D[31:16]#
FSB1D[47:32]#
FSB1D[63:48]#
FSB1D[15:0]#
Data Group
FSB1DSTB{P/N}[0]#
FSB1DSTB{P/N}[1]#
FSB1DSTB{P/N}[2]#
FSB1DSTB{P/N}[3]#
Data Strobe
Description
Intel
®
5100 Memory Controller Hub Chipset
Bus Inversion Signal
FSB1DBI[0]#
FSB1DBI[1]#
FSB1DBI[2]#
FSB1DBI[3]#
Datasheet
41