HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 127

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
Table 54.
July 2009
Order Number: 318378-005US
GIO Port Mode Selection (Sheet 1 of 2)
Device:
Function:
Offset:
13:11
10:8
7
6:4
3:1
0
GPMNXT0[2:0]
3'b000
3'b001
3'b010
Bit
(IOU0)
RO
RO
RO
RWST
RWST
RWST
Attr
®
5100 MCH Chipset
0
0
40h
000
000
0
000
000
0
Default
GIO Port (IOU0)
x4
invalid
x4
Port0
(ESI)
GPMCUR1: IOU1 max width Current Configuration Now (ports 4-7)
This field is updated by the hardware to indicate the current link width of IOU1
ports that is used for training. This field is set before training gets underway.
000: x4, x4, x4, x4
001: x8, --, x4, x4
010: x4, x4, x8, --
011: x8, --, x8, --
100: x16, --, --, --, --
111: Auto negotiation
others: Reserved
GPMCUR0: IOU0 max width Current Configuration (ports 2-3 only, port 0,
ESI, is always x4)
This field is updated by the hardware to indicate the current link width of IOU1
ports that is used for training. This field is set before training gets underway.
000: x4, x4
001: Reserved
010: x8, --
111: Auto Negotiation
Others: Reserved
LWTM: Link Width Training Mode
This field is updated by the hardware to provide feedback to software on the
training mode it is using following reset, i.e., link strap or soft initialization of link
widths.
0: IOU clusters trained the links using the PEWIDTH[3:0] pins (external strapping)
[default]
1: IOU clusters trained the links using the soft initialization mechanism in this
register viz. GPMNXT1 and GPMNXT0 following a hard reset.
GPMNXT1: IOU1 max width Configuration Next (ports 4-7)
The IOU1 cluster will use this field to train the link after a hard reset provided
LWOEN is set.
Refer to
GPMNXT0: IOU0 max width Configuration Next (ports 2-3)
The IOU0 cluster will use this field to train the links after a hard reset provided
LWOEN is set.
Refer to
LWOEN: Link Width over-ride Enable
0: Disables software from setting the PCI Express* link width through this register
and the Link width is controlled by the external pins PEWIDTH[3:0]. (default).
1. Enables BIOS/Software to set the required link width through this register. When
this bit is set, the IOU cluster will ignore the external pin strap (PEWIDTH[3:0] and
use the described table for configuring the link width. The values will take effect
after a hard reset.
RSVD
RSVD
(RSVD)
Port1
Table 54, “GIO Port Mode Selection.”
Table 54, “GIO Port Mode Selection.”
x4
x8
Port2
x4
N/A
Port3
GPMNXT1[2:0]
3'b000
3'b001
3'b010
Description
(IOU1)
Intel
®
5100 Memory Controller Hub Chipset
GIO Port (IOU1)
x4
x8
x4
Port4
x4
N/A
x4
Port5
x4
x4
x8
Port6
Datasheet
x4
x4
N/A
Port7
127