HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 313

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Functional Description—Intel
Table 96.
5.13.5
Figure 28.
July 2009
Order Number: 318378-005US
Options and Limitations (Sheet 2 of 2)
PCI Express* Port Physical Layer Characteristics
The PCI Express* physical layer implements high-speed differential serial signaling
using the following techniques:
Figure 28, “PCI Express* Packet Visibility By Physical Layer”
physical layer on a PCI Express* packet. There are two types of packets: Link layer
packets and Transaction Layer Packets. The physical layer is responsible for framing
these packets with STP/END symbols (Transaction Layer Packets) and SDP/END
symbols (Data Link Layer packets). The grayed out segment is not decoded by the
Physical layer.
PCI Express* Packet Visibility By Physical Layer
Traffic Streams
Isochrony
ECRC
Ordering
No Snoop
Power Management
No Cable Support & no repeaters
Poisoning
• Differential signaling (1.6 V peak-to-peak)
• 2.5 GHz data rate (up to 2 GB/s/direction peak bandwidth for a x8 port)
• 8b/10b encoding for embedded clocking and packet framing
• Unidirectional data path in each direction supporting full duplex operation
• Random idle packets and spread-spectrum clocking for reduced EMI
• Loop-back mode for testability
• Lane reversal
• Polarity Inversion
Parameter
®
5100 MCH Chipset
STP
SDP
Link/Txn Layer Visible Info
Link Layer Visible Info
The MCH does not support two streams of two priority levels (High/low) on
the PCI Express* ports 2 and 3. All of the ports support only one stream
and one priority level (including the ESI) on VC0.
MCH does not support isochrony
The MCH does not support ECRC
The MCH only supports strict PCI ordering
The MCH will not snoop processor caches for transactions with the No
Snoop attribute
The MCH cannot be powered down, but will forward messages, generate
PME_Turn_Off and collect PME_TO_Acks. It will provide the PM Capabilities
structure. The MCH does not support Active State Power Management nor
the L0s state.
Retry buffers are sized to meet the Intel
for an integrated DP chassis and which do not require cable or repeater
support. Only an internal trace connector latency of 20 in. of FR4 is
assumed.
MCH will poison data that it cannot correct
Intel
Support
®
5100 Memory Controller Hub Chipset
®
illustrates the scope of the
5100 MCH Chipset requirements
END
END
Datasheet
313