HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 137

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.8.10.2
3.8.10.3
3.8.10.4
July 2009
Order Number: 318378-005US
MSINXPTR[7:2,0]- MSI Next Pointer
MSICTRL[7:2,0] - Message Control Register
MSIAR[7:2,0] - MSI Address Register
The MSI Address Register (MSIAR) contains the system specific address information to
route MSI interrupts and is broken into its constituent fields.
Device:
Function:
Offset:
Device:
Function:
Offset:
Device:
Function:
Offset:
31:20
19:12
15:8
7:0
6:4
3:1
Bit
Bit
Bit
7
0
®
Attr
Attr
Attr
RW
RW
RW
RO
RO
RO
RO
RV
5100 MCH Chipset
7-2, 0
0
59h
7-2, 0
0
5Ah
7-2, 0
0
5Ch
Default
Default
Default
FEEh
6Ch
00h
000
000
00h
0
0
NXTPTR: Next Pointer
This field is set to 6Ch for the next capability list (PCI Express* capability
structure - PEXCAP) in the chain.
Reserved.
AD64CAP: 64-bit Address Capable
This field is hardwired to 0h since the message writes addresses are only 32-
bit addresses (e.g., FEEx_xxxxh).
MMEN: Multiple Message Enable
Software writes to this field to indicate the number of allocated messages
which is aligned to a power of two. When MSI is enabled, the software will
allocate at least one message to the device. See below for discussion on how
the interrupts are handled if N is the number of messages by software.
If software writes a value greater than the limit specified by the MMCAP field in
the MMEN field, it is considered as a programming error.
MMCAP: Multiple Message Capable
Software reads this field to determine the number of requested messages,
which is aligned to a power of two. It is set to 1 message (encoding of 000).
MSIEN: MSI Enable
The software sets this bit to select legacy interrupts or transmit MSI
messages.
0: Disables MSI from being generated.
1: Enables the Intel
context specific service for events such as PCI Hot Plug*, PM and RAS.
AMSB: Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address.
ADSTID: Address Destination ID
This field is initialized by software for routing the interrupts to the appropriate
destination.
®
5100 MCH Chipset to use MSI messages to request
Description
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
137