HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 251

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Register Description—Intel
3.12
3.12.0.1
3.12.0.2
July 2009
Order Number: 318378-005US
PCI Express* Per-Port Registers
Table 74
map for each port that supports DMA Engine functionality. These registers control the
PCI Express* proprietary enhancements. Each port which implements DMA Engine
Technology is required to have a set of these registers located in the DMA Engine
device’s MMIO space.
Under some existing operating systems (e.g., Microsoft Windows*), a device driver is
only allowed to access its own PCI configuration space, not the configuration space of
any other device. This is why the per-port stream ID register sets exist in the memory
mapped I/O (MMIO) space. This avoids having a separate PCI filter device driver
(instance) on each of the PCI-to-PCI bridges and solves the problem of the OS
remapping PCI Bridge MMIO space.
It also avoids the need for providing inbound configuration access, besides easier for
resource reallocation (PCI Hot Plug*).
NXTPPRSET2 - Next Per Port Register Set
The per-port offset indicates where the next set of per-port registers resides in the
MMIO space. This register points to the next set of per-port registers and provides the
means for S/W to locate all of the per-port MMIO register sets.
NXTPPRSET3 - Next Per Port Register Set
Offset:
0
Offset:
Offset:
15:2
15:2
1:0
1:0
Bit
Bit
Bit
RWST
Attr
Attr
RO
RO
RV
RV
®
lists the standard registers added to the DMA Engine device’s MMIO address
Attr
5100 MCH Chipset
22Ch, 1ACh, 12Ch, ACh
300h
380h
Default
Default
00E0h
0
Default
00
0h
0
Nxt_PP_Offset: Next Per port offset
This value added to the CB_BAR value provides the memory address of the next set
of per-port registers for port 3. Since the Per port offset is 32-bit aligned, the
effective address is calculated by concatenating “00E0h” (bits 7, 8, 9 are ‘1’s) with
“00b” giving 380h as an offset from CB_BAR and this locates the port priority
registers for port 3 in the map.
Reserved
Nxt_PP_Offset: Next Per port offset
This is the last per-port register set (port 3) in the linked list and hence this value is
0h.
Reserved
DMA_trans_saddr_err_Msk: DMA Transfer Source Address Error Mask
Description
Description
Description
Intel
®
5100 Memory Controller Hub Chipset
Datasheet
251