HH80556KH0364M S LAGD Intel, HH80556KH0364M S LAGD Datasheet - Page 166

• Manufacturer Part Number: HH80556KH0364M S LAGD
• Manufacturer: Intel

Specifications of HH80556KH0364M S LAGD

• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

3.8.12.18
3.8.12.19
Intel
Datasheet
166
®
5100 Memory Controller Hub Chipset
SCSPCAPID[7:2,0] - Intel
specific Capability ID
This register identifies the capability structure and points to the next structure.
PEX_ERR_DOCMD[7:2,0] - PCI Express* Error Do Command Register
Link Error Commands for doing the various signaling: ERR[2:0] and MCERR.
Device:
Function:
Offset:
Device:
Function:
Offset:
31:20
19:16
15:0
31:8
7:6
5:4
3:2
1:0
Bit
Bit
Attr
RO
RO
RO
Attr
RW
RW
RW
RW
RV
7-2, 0
0
140h
7-2, 0
0
144h
Default
Default
0h
0h
0h
0h
00
00
00
00
NXTCAPOFF: Next Capability Offset
This field points to the next Capability in extended configuration space. It is
set 000h since this is the final structure in the chain.
VN: Version Number
Version number for this capability structure
EXTCAPID: Extended CAP_ID
Reserved
PEX_RP_FAT_MAP: Root Port steering for fatal errors
00: ERR[0]
01: ERR[1]
10: ERR[2]
11: MCERR
The Root Port Fatal errors are routed to one of the ERR[2:0] pins or MCERR.
PEX_RP_NF_MAP: Root Port steering for non-fatal errors
00: ERR[0]
01: ERR[1]
10: ERR[2]
11: MCERR
The Root Port Non Fatal (uncorrectable) errors are routed to one of the
ERR[2:0] pins or MCERR.
PEX_RP_CORR_MAP: Root Port steering for correctable errors
00: ERR[0]
01: ERR[1]
10: ERR[2]
11: MCERR
The Root Port correctable errors are routed to one of the ERR[2:0] pins or
MCERR.
PEX_DEV_UNSUP_MAP:
Report steering for unsupported request errors (master aborts) for legacy
devices
00: ERR[0]
01: ERR[1]
10: ERR[2]
11: MCERR
Unsupported request error report enable is in the Device control register. This
is Error IO2.
®
5100 Memory Controller Hub Chipset-
Intel
®
Description
5100 MCH Chipset—Register Description
Description
Order Number: 318378-005US
July 2009