MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 97

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
Bit Name
BWE
4–3
WP
1–0
5
2
The Buffered Write Enable bit defines the value for enabling buffered writes. If BWE = 0, the termination of an
operand write cycle on the processor's local bus is delayed until the external bus cycle is completed. If BWE = 1,
the write cycle on the local bus is terminated immediately and the operation is then buffered in the bus controller. In
this mode, operand write cycles are effectively decoupled between the processor's local bus and the external bus.
Generally, the enabling of buffered writes provides higher system performance but recovery from access errors may
be more difficult. For the ColdFire CPU, the reporting of access errors on operand writes is always imprecise, and
enabling buffered writes simply decouples the write instruction from the signaling of the fault even more.
0 Don’t buffer writes
1 Buffer writes
Reserved, should be cleared.
The Write Protect bit defines the write-protection attribute. If the effective memory attributes for a given access
select the WP bit, an access error terminates any attempted write with this bit set.
0 Read and write accesses permitted
1 Only read accesses permitted
Reserved, should be cleared.
Table 5-6. Access Control Registers Field Descriptions (continued)
MCF5253 Reference Manual, Rev. 1
Description
Instruction Cache
5-9