MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 479

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
Field
ASE
PSE
RST
3–2
FS
RS
5
4
1
0
Asynchronous Schedule Enable. This bit controls whether the controller skips processing the Asynchronous
Schedule. Used only in host mode.
1 Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
0 Do not process the Asynchronous Schedule.
Periodic Schedule Enable. This bit controls whether the controller skips processing the Periodic Schedule. Used only
in host mode.
1 Use the PERIODICLISTBASE register to access the Periodic Schedule.
0 Do not process the Periodic Schedule.
Frame List Size. Together with bit 15 these bits make the FS[2:0] field. This field is Read/Write only if Programmable
Frame List Flag in the HCCPARAMS registers is set to 1. This field specifies the size of the frame list that controls
which bits in the Frame Index Register should be used for the Frame List Current index. Used only in host mode.
Note: Values below 256 elements are not defined in the EHCI specification.
000 1024 elements (4096 bytes)
001 512 elements (2048 bytes)
010 256 elements (1024 bytes)
011 128 elements (512 bytes)
100 64 elements (256 bytes)
101 32 elements (128 bytes)
110 16 elements (64 bytes)
111 8 elements (32 bytes)
Controller Reset. The software uses this bit to reset the controller. This bit is cleared by the controller when the reset
process is complete. The software cannot terminate the reset process early by writing a zero to this register.
Host Mode:
When the software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state
machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB
reset is not driven on downstream ports. The software should not set this bit to a one when the HCHalted bit in the
USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior.
Device Mode:
When the software writes a one to this bit, the controller resets its internal pipelines, timers, counters, state machines
etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. Writing a one to this
bit in device mode is not recommended.
Run/Stop.
Host Mode:
When set to a 1, the controller proceeds with the execution of the schedule. The controller continues execution as
long as this bit is set. When this bit is set to 0, the Host Controller completes the current transaction on the USB and
then halts. The HC Halted bit in the status register indicates when the Host Controller has finished the transaction
and has entered the stopped state. The software should not write a one to this field unless the controller is in the
Halted state (that is, HCHalted in the USBSTS register is a one).
Device Mode:
Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. This control bit
is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed
mode. The software should use this bit to prevent an attach event before the controller has been properly initialized.
Writing a 0 to this will cause a detach event.
1 Run.
0 Stop.
Table 24-15. USB Command Register (USBCMD) Register Field Descriptions (continued)
MCF5253 Reference Manual, Rev. 1
Description
Universal Serial Bus Interface
24-17