MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 597

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

24.11.3.3.2 Priming Receive Endpoints
Priming receive endpoints is identical to priming of transmit endpoints from the point of view of the DCD.
At the device controller the major difference in the operational model is that there is no data movement of
the leading packet data simply because the data is to be received from the host.
Note as part of the architecture, the FIFO for the receive endpoints is not partitioned into multiple channels
like the transmit FIFO. Thus, the size of the RX FIFO does not scale with the number of endpoints.
24.11.3.4 Interrupt/Bulk Endpoint Operational Model
The behaviors of the device controller for interrupt and bulk endpoints are identical. All valid IN and OUT
transactions to bulk pipes will handshake with a NAK unless the endpoint had been primed. Once the
endpoint has been primed, data delivery will commence.
A dTD will be retired by the device controller when the packets described in the transfer descriptor have
been completed. Each dTD describes N packets to be transferred according to the USB Variable Length
transfer protocol. The
controller computes the number and length of the packets to be sent/received by the USB vary according
to the total number of bytes and maximum packet length.
TX-dTD is complete when:
Freescale Semiconductor
With Zero Length Termination (ZLT) = 0
With Zero Length Termination (ZLT) = 1
Bytes (dTD)
Bytes (dTD)
The MULT field in the dQH must be set to ‘00’ for bulk, interrupt, and
control endpoints.
511
512
512
511
512
512
Table 24-83. Variable Length Transfer Protocol Example (ZLT=0)
Table 24-84. Variable Length Transfer Protocol Example (ZLT=1)
Equation
N = MAXINT (Number of Bytes/Maximum Packet Length )
N = INT (Number of Bytes/Maximum Packet Length) + 1
Max. Packet Length (dQH)
Max. Packet Length (dQH)
and
256
256
512
Equation
MCF5253 Reference Manual, Rev. 1
256
256
512
and
NOTE
Table 24-83
N
2
2
1
N
2
3
2
and
256
256
512
P1
256
256
512
P1
Table 24-84
255
256
P2
–
255
256
P2
0
describe how the device
Universal Serial Bus Interface
P3
–
–
–
P3
–
0
–
Eqn. 24-1
Eqn. 24-2
24-135