MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 238

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

DMA Controller
14-10
S_RW
SSIZE
27–25
21–20
DINC
Field
BWC
SINC
DAA
24
23
22
19
The three bandwidth control bits are decoded for internal bandwidth control. When the byte count reaches any
multiple of the programmed BWC boundary, the request signal to the internal arbiteris negated until data access
completes. This enables the arbiter to give another device access to the
bits. When the bits are cleared, the DMA does not negate its request. The 000 encoding asserts a priority signal
when the channel is active, signaling that the transfer has been programmed for a higher priority. When the BCR
reaches a multiple of the values shown in
For example, if BWC = 001 (512 bytes or value of 0x0200), BCR24BIT = 0, and the BCR is set to 0x1000, the bus is
relinquished after BCR values of 0x2000, 0x1E00, 0x1C00, 0x1A00, 0x1800, 0x1600, 0x1400, 0x1200, 0x1000,
0x0E00, 0x0C00, 0x0A00, 0x0800, 0x0600, 0x0400, and 0x0200. In another example, BWC = 110, BCR24BIT = 0,
and the BCR is set to 33000. The bus is relinquished after transferring 232 bytes, because the BCR is at 32768,
which is a multiple of 16384.
Dual address access.
0 The DMA channel is in dual-address mode.
1 Reserved.
Reserved, must be set to 0.
The source increment bit determines whether the source address increments after each successful transfer.
0 No change to the SAR after a successful transfer.
1 The SAR increments by 1, 2, 4, or 16; depending upon the size of the transfer.
The source size field determines the data size of the source bus cycle for the DMA control module.
shows the encoding for this field.
The destination increment bit determines whether the destination address increments after each successful transfer.
0 No change to the DAR after a successful transfer.
1 The DAR increments by 1, 2, 4, or 16; depending upon the size of the transfer.
Table 14-8. DMA Control Register (DCR) Field Descriptions (continued)
MCF5253 Reference Manual, Rev. 1
BWC
000
001
010
011
100
101
110
111
Table 14-10. SSIZE Encoding
SSize
Table 14-9. BWC Encoding
Table
00
01
10
11
BCR24BIT = 0
14-9, the bus is relinquished.
16384
32768
Description
1024
2048
4096
8192
512
DMA has priority
Block Size
Transfer Size
BCR24BIT = 1
Longword
1048576
131072
262144
524288
Word
16384
32768
65536
Byte
Line
bus.Table 14-9
shows the encoding for these
Freescale Semiconductor
Table 14-10