MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 543

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Activation of the list is simple. The system software writes the physical memory address of a queue head
into the ASYNCLISTADDR register, then enables the list by setting the Asynchronous Schedule Enable
bit in the USBCMD register to a one.
When inserting a queue head into an active list, the software must ensure that the schedule is always
coherent from the host controllers' point of view. This means that the system software must ensure that all
queue head pointer fields are valid. For example qTD pointers have T-Bits set or reference valid qTDs and
the Horizontal Pointer references a valid queue head data structure. The following algorithm represents the
functional requirements:
24.9.9.2
This is a software requirement section. There are two independent events for removing queue heads from
the asynchronous schedule. The first is shutting down (deactivating) the asynchronous list. The second is
extracting a single queue head from an activated list. The software deactivates the asynchronous schedule
by setting the Asynchronous Schedule Enable bit in the USBCMD register to a zero. The software can
determine when the list is idle when the Asynchronous Schedule Status bit in the USBSTS register is
cleared. The normal mode of operation is that the software removes queue heads from the asynchronous
schedule without shutting it down. The software must not remove an active queue head from the schedule.
The software should first deactivate all active qTDs, wait for the queue head to go inactive, then remove
the queue head from the asynchronous list. The software removes a queue head from the asynchronous list
using the following algorithm. The software merely must ensure all of the link pointers reachable by the
host controller are kept consistent.
Freescale Semiconductor
InsertQueueHead (pQHeadCurrent, pQueueHeadNew)
End InsertQueueHead
UnlinkQueueHead (pQHeadPrevious, pQueueHeadToUnlink, pQHeadNext)
--
-- Requirement: all inputs must be properly initialized.
--
-- pQHeadCurrent is a pointer to a queue head that is
-- already in the active list
-- pQHeadNew is a pointer to the queue head to be added
--
-- This algorithm links a new queue head into a existing
-- list
--
pQueueHeadNew.HorizontalPointer = pQueueHeadCurrent.HorizontalPointer
pQueueHeadCurrent.HorizontalPointer = physicalAddressOf(pQueueHeadNew)
--
-- Requirement: all inputs must be properly initialized.
--
-- pQHeadPrevious is a pointer to a queue head that
-- references the queue head to remove
-- pQHeadToUnlink is a pointer to the queue head to be
-- removed
-- pQheadNext is a pointer to a queue head still in the
-- schedule. Software provides this pointer with the
-- following strict rules:
-- if the host software is one queue head, then
-- pQHeadNext must be the same as
-- QueueheadToUnlink.HorizontalPointer. If the host
Removing Queue Heads from Asynchronous Schedule
MCF5253 Reference Manual, Rev. 1
Universal Serial Bus Interface
24-81