MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 519

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

1
Queue Element Transfer Descriptors must be aligned on 32-byte boundaries.
24.8.5.1
The first DWord of an element transfer descriptor is a pointer to another transfer element descriptor.
24.8.5.2
The second DWord of a queue element transfer descriptor is used to support hardware-only advance of the
data stream to the next client buffer on short packet. To be more explicit the host controller will always use
this pointer when the current qTD is retired due to short packet.
Freescale Semiconductor
dt
31–5 Next qTD
31–5 Alternate Next
31
4–1
Bit
Bit
Host controller read/write; all others read-only.
1
0
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Pointer
qTD Pointer
Name
–
T
Name
Next qTD Pointer
Alternate Next qTD Pointer
This field contains the physical memory address of the next qTD to be processed. The field corresponds to
memory address signals[31–5], respectively.
Reserved. These bits are reserved and their value has no effect on operation.
Terminate. This bit indicates to the Host Controller that there are no more valid entries in the queue.
0 Pointer is valid (points to a valid Transfer Element Descriptor).
1 Pointer is invalid.
Total Bytes to Transfer
This field contains the physical memory address of the next qTD to be processed in the event that the
current qTD execution encounters a short packet (for an IN transaction). The field corresponds to
memory address signals [31–5], respectively.
Table 24-52. qTD Alternate Next Element Transfer Pointer (DWord 1)
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
Table 24-51. qTD Next Element Transfer Pointer (DWord 0)
Figure 24-40. Queue Element Transfer Descriptor (qTD)
Alternate Next qTD Pointer
Next qTD Pointer
1
MCF5253 Reference Manual, Rev. 1
ioc C_Page
15
14 13 12 11 10
Description
Description
1
Cerr
1
Code
9
PID
8
0000_0000_0000
0000_0000_0000
0000_0000_0000
0000_0000_0000
Current Offset
7
6
Universal Serial Bus Interface
5
Status
4
1
0000
0000
3
1
2
1
T
T
0
Offset
0x0C
0x1C
0x00
0x04
0x08
0x10
0x14
0x18
24-57