MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 609

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

1
24.11.6 Servicing Interrupts
The interrupt service routine must consider that there are high-frequency, low-frequency operations, and
error operations and order accordingly.
24.11.6.1 High-Frequency Interrupts
High frequency interrupts in particular should be handed in the order below. The most important of these
is listed first because the DCD must acknowledge a setup buffer in the timeliest manner possible.
24.11.6.2 Low-Frequency Interrupts
The low frequency events include the following interrupts. These interrupt can be handled in any order
since they don't occur often in comparison to the high-frequency interrupts.
24.11.6.3 Error Interrupts
Error interrupts will be least frequent and should be placed last in the interrupt service routine.
Freescale Semiconductor
USB Error Interrupt This error is redundant because it combines USB Interrupt and an error status in the dTD. The DCD will
System Error
Execution
It is likely that multiple interrupts to stack up on any call to the Interrupt Service Routine AND during the Interrupt Service
Routine.
Order
1a
1b
Interrupt
2
Port Change
Sleep Enable (Suspend)
Reset Received
USB Interrupt
ENDPTSETUPSTATUS
USB Interrupt
ENDPTCOMPLETE
SOF Interrupt
more aptly handle packet-level errors by checking dTD status field upon receipt of USB Interrupt
(w/ ENDPTCOMPLETE).
Unrecoverable error. Immediate Reset of core; free transfers buffers in progress and restart the DCD.
Interrupt
Interrupt
1
Table 24-91. Low Frequency Interrupt Events
Table 24-90. Interrupt Handling Order
Copy contents of setup buffer and acknowledge setup packet (as indicated in
Section 24.11.4, “Managing Queue
2.0 Chapter 9 or application specific protocol.
Handle completion of dTD as indicated in
Action as deemed necessary by application. This interrupt may not have a use in all
applications.
Change the software state information.
Change the software state information. Low power handling as
necessary.
Change the software state information. Abort pending transfers.
Table 24-92. Error Interrupt Events
MCF5253 Reference Manual, Rev. 1
Action
Action
Heads”). Process setup packet according to USB
Action
Section 24.11.4, “Managing Queue
Universal Serial Bus Interface
Heads”.
24-147