MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 359

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

END
EMASTX
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last byte of data, which can be done by setting the transmit acknowledge bit (TXAK)
before reading the next-to-last byte of data. Before reading the last byte of data, a STOP signal must first
be generated. The following code is an example showing how a master receiver generates a STOP signal.
MASR
LAMAR
ENMASR
NXMAR
18.6.5
At the end of data transfer, if the master still wants to communicate on the bus, it can generate another
START signal followed by another slave address without first generating a STOP signal. A program
example follows.
RESTART MOVE.B
18.6.6
In the slave interrupt service routine, the module that is addressed as slave bit (IAAS), should be tested to
check if a calling of its own address was received. If IAAS is set, software should set the transmit/receive
mode select bit (MTX bit of MBCR) according to the R/W command bit (SRW). Writing to the MBCR
clears the IAAS automatically. The only time IAAS is read as set is from the interrupt at the end of the
address cycle where an address match occurred; interrupts resulting from subsequent data transfers will
have IAAS cleared. A data transfer can now be initiated by writing information to MBDR, for slave
transmits, or read from MBDR, in slave-receive mode. A dummy read of the MBDR in slave/receive mode
will release SCL, allowing the master to transmit data.
In the slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting
the next byte of data. Setting RXAK means an “end-of-data’' signal from the master receiver, after which
it must be switched from transmitter mode to receiver mode by software. A read from MBDR then releases
the SCL line so that the master can generate a STOP signal.
Freescale Semiconductor
MOVE.B
BRA.S
LEA.L
BCLR.B
RTE;
MOVE.B
SUBQ.L
MOVE.B
BEQ.S
MOVE.B
EXTB.L
SUBI.L
BNE.S
BSET.B
BRA
BCLR.B
MOVE.B
BSET.B
MOVE.B
MOVE.B
MOVE.B
MOVE.B
Generation of Repeated START
Slave Mode
D0,TXCNT
EMASTX
MBCR,-(A7)
#5,(A7)+
RXCNT,D0
#1,D0
D0,RXCNT
ENMASR
RXCNT,D1
D1
#1,D1
NXMAR
#3,MBCR
NXMAR
#5,MBCR
MBDR,RXBUF
MBCR,-(A7)
#2, (A7)
(A7)+, MBCR
CALLING,-(A7)
CALLING,-(A7)
(A7)+, MBDR
MCF5253 Reference Manual, Rev. 1
;Exit
;Generate a STOP condition
Return from interrupt
;Decrease RXCNT
;Last byte to be read
;Check second-to-last byte to be read
;
; Not last one or second last
;Disable ACK
; Last one, generate 'STOP'signal
; Read data and store RTE
; Another START (RESTART)
;Transmit the calling address, D0=R/W-
;
I
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C Modules
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