MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 400

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Background Debug Mode (BDM) Interface
20.5.1
The address breakpoint registers (ABLR and ABHR) define a region in the operand address space of the
processor that can be used as part of the trigger. The full 32-bits of the ABLR and ABHR values are
compared with the address for all transfers on the processor’s high-speed local bus. The trigger definition
register (TDR) determines if the trigger is the inclusive range bound by ABLR and ABHR, all addresses
outside this range, or the address in ABLR only. The ABHR is accessible in supervisor mode as debug
control register $C using the WDEBUG instruction and through the BDM port using the RDMREG and
WDMREG commands. The ABLR is accessible in supervisor mode as debug control register $D using the
WDEBUG instruction and through the BDM port using the WDMREG commands. The ABHR is
overwritten by the BDM hardware when accessing memory as described in
Module Hardware.”
ADDRESS[31:0]–Low Address
This field contains the 32-bit address which marks the lower bound of the address breakpoint range.
Additionally, if a breakpoint on a specific address is required, the value is programmed into the ABLR.
20-30
Reset
Reset
W
W
R
R
31
15
–
–
Address Breakpoint Registers
31
30
14
–
–
29
13
–
–
Figure 20-29. Address Breakpoint Low Register (ABLR)
28
12
–
–
Figure 20-28. Debug Programming Mode
27
11
–
–
15
15
MCF5253 Reference Manual, Rev. 1
26
10
–
–
25
–
–
9
7
ADDRESS[31:0]
ADDRESS[31:0]
24
–
–
8
0
0
23
–
–
7
ABLR
BAAR
ABHR
AATR
PBR
PBMR
DBR
DBMR
TDR
CSR
22
–
–
6
Address
Breakpoint Registers
Address Attribute
Trigger Register
PC Breakpoint
Registers
Configuration/Status Register
BDM ADDRESS Attribute
Register
Data Breakpoint
Registers
Trigger Definition
Register
21
–
–
5
Section 20.4.1.2, “Debug
20
–
–
4
19
–
–
3
Freescale Semiconductor
Access: User write only
18
–
2
–
17
–
–
1
16
–
–
0