MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 430

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Advanced Technology Attachment Controller (ATA)
23.4
See
23.4.1
For a detailed description of the ATA bus signal, refer to the ATA-6 specification.
23.4.1.1
This signal is the ATA reset signal. When low, the ATA bus is in reset state. When high, no reset. The ATA
bus is in reset whenever the appropriate bit in the control register is cleared. After system reset, the ATA
bus is in reset.
23-4
Table 23-1
It is the task of the host CPU or the host smart DMA unit to read data or write data to the FIFO to
keep the transfer going. Normal set-up is that the host (smart) DMA unit takes on this task. For this
purpose, the fifo_rcv_alarm and fifo_tx_alarm signals are sent to the host DMA unit.
fifo_rcv_alarm informs the host DMA unit that there is at least 1 packet of data waiting in the FIFO
to be read by the host DMA. Whenever this signal is high, the host DMA should transfer one packet
of data from the FIFO to the main memory. Typical packet size is 32 bytes (8 long words), but other
packet sizes can be handled too. fifo_tx_alarm informs the host DMA unit that there is space for at
least 1 packet to be written by the host DMA. Whenever this signal is high, the host DMA should
transfer one packet of data from main memory to the FIFO. Typical packet size is 32 bytes (8 long
words), but other packet sizes can be handled too.
External Signal Description
Detailed Signal Descriptions
ATA_RST (Out)
for the list of signals entering and exiting this module to peripherals within the device.
ATA_RST
ATA_DIOR
ATA_DIOW
ATA_CS1
ATA_CS0
ATA_A2
ATA_A1
ATA_A0
ATA_DMARQ
ATA_DMACK
ATA_INTRQ
ATA_IORDY
ATA_D[15:0]
1
This signal is a standard ATA bus signal. It conforms with the ATA specification.
Name
ATA bus reset signal. Active low. If active,
ATA bus DMA acknowledge
ATA data bus (little-endian)
MCF5253 Reference Manual, Rev. 1
ATA bus interrupt request
Table 23-1. Signal Properties
ATA bus address line 2
ATA bus address line 1
ATA bus address line 0
ATA bus DMA request
ATA bus chip select 1
ATA bus chip select 0
ATA bus write strobe
ATA bus read strobe
ata device is reset
ATA bus iordy
Function
1
Reset State
HI_Z
0
1
1
0
0
0
–
1
–
–
1
1
Tri-state I/O
Direction
O
O
O
O
O
O
O
O
O
O
I
I
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