MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 118

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Synchronous DRAM Controller Module
7.4.5
The DRAM controller is equipped with a refresh counter and control. This logic is responsible for
providing timing and control to refresh the SDRAM. Once the refresh counter is set, and refresh is enabled,
the counter counts to zero. At this time, an internal refresh request flag is set and the counter begins
counting down again. The DRAM controller completes any active burst operation and then performs a
PALL
refresh cycle includes a delay from any precharge to the auto-refresh command, the auto-refresh
command, and then a delay until any
auto-refresh cycle is delayed until the cycle is completed.
Figure 7-10
request becomes active. The request is delayed by the precharge to
SDRAM bank by the CAS bits. The
DCR[RTIM] is inserted before the next
is initiated, but does not generate an SDRAM access until T
7-14
operation. The DRAM controller then initiates a refresh cycle and clears the refresh request flag. This
D[31:16]
SDRAS
SDCAS
SD_CS0]
A[31:0]
XDQM
SDWE
BCLK
Auto-Refresh Operation
shows the auto-refresh timing. In this case, there is an SDRAM access when the refresh
Figure 7-9. Synchronous, Continuous Page-Mode Access—Read after Write
ACTV
t
RCD
Row
= 3
NOP
REF
ACTV
MCF5253 Reference Manual, Rev. 1
ACTV
command is then generated and the delay required by
WRITE
Column
command is allowed. Any SDRAM access initiated during the
command is generated. In this example, the next bus cycle
NOP
READ
RC
is finished.
Column
t
CASL
ACTV
NOP
= 2
delay programmed into the active
NOP
NOP
Freescale Semiconductor
t
EP
PALL