MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 87

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Note: MCLK1 will output a clock signal just after reset, it can be configured as GPIO if so desired. The frequency of the clock will
Note: The AUDIO_CLOCK can also be derived from the LRCK3/AUDIOCLK/GPIO43 pin.
The multiplexer that switches AUDIO_CLOCK between CRIN and CRIN/2 is glitch free. No reset is
needed after switching audio clock. For the MCLK1 and MCLK2 clocks, the divide by 2 is 50% duty
cycle, divide by 3 is 33% duty cycle, and divide by 4 is 50% duty cycle.
4.5
To save power, it is recommended that users reduce the frequency of the CPU clocks. This is done by
reprogramming the PLLCONFIG register.
The PLL is also configured with a power down bit. This bit, when set to 1, this sets the PLL to Sleep mode.
In Sleep mode, the VCXO is turned off.
4.6
The device can be put in a low power Sleep mode, where all internal clocks and all on-chip functions are
stopped. In Sleep mode, the only block still functional is the on-chip voltage regulator. All the other analog
features are put in to low-power operation and all digital functions are stopped.
Freescale Semiconductor
be the same as CRIN prior to initialization of the PLL.
PLLCR[CLSEL]
Reduced Power Mode
Sleep / Wake-up Mode
(Bits 30–28)
011
100
101
110
111
000
001
010
011
100
101
110
111
The PLL must go through the re-locking procedure when it is re-enabled.
PllCR CRsel
(Bit 23)
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 4-7. PLLCR Bit Fields (continued)
MCF5253 Reference Manual, Rev. 1
pllCR Config
Audiosel
(Bit 22)
1
1
1
1
1
0
0
0
0
0
0
0
0
NOTE
AUDIO_CLOCK
CRIN/2
CRIN/2
CRIN/2
CRIN/2
CRIN/2
CRIN/2
CRIN/2
CRIN/2
CRIN
CRIN
CRIN
CRIN
CRIN
MCLK2
CRIN/2
CRIN/2
CRIN/2
CRIN/2
CRIN/2
CRIN/2
CRIN/2
CRIN
CRIN
CRIN
CRIN
CRIN
CRIN
Phase-Locked Loop and Clock Dividers
MCLK1
CRIN/2
CRIN/2
CRIN/2
CRIN/2
CRIN/2
CRIN/2
CRIN
CRIN
CRIN
CRIN
CRIN
CRIN
CRIN
4-7