MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 294

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Queued Serial Peripheral Interface (QSPI) Module
The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48 separate
locations that comprise 16 words of transmit data, 16 words of receive data and 16 bytes of commands.
A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR]. This also causes
the value in QAR to increment.
Correspondingly, a read at QDR returns the data in the RAM at the address specified by QAR[ADDR].
This also causes QAR to increment. A read access requires a single wait state.
16.4.5
The QAR, shown in
operations affect.
16.4.6
The QDR, shown in
data from and to the QSPI RAM through this register.
16-12
Address MBAR + 0x410
WCEF
ABRT
Field
SPIF
Reset
3
2
1
0
W
R
Write collision error flag. Indicates that an attempt has been made to write to the RAM entry that is currently being
executed. Writing a 1 to this bit clears it and writing 0 has no effect.
Abort flag. Indicates that QDLYR[SPE] has been cleared by the user writing to the QDLYR rather than by completion
of the command queue by the QSPI. Writing a 1 to this bit clears it and writing 0 has no effect.
Reserved, should be cleared.
QSPI finished flag. Asserted when the QSPI has completed all the commands in the queue. Set on completion of the
command pointed to by QWR[ENDQP], and on completion of the current command after assertion of QWR[HALT].
In wraparound mode, this bit is set every time the command pointed to by QWR[ENDQP] is completed. Writing a 1 to
this bit clears it and writing 0 has no effect.
15
0
QSPI Address Register (QAR)
QSPI Data Register (QDR)
The QAR does not wrap after the last queue entry within each section of the
RAM.
14
0
Table 16-6. QSPI Interrupt Register (QIR) Field Descriptions (continued)
Figure
Figure
13
0
16-8, is used to specify the location in the QSPI RAM that read and write
16-9, is used to access QSPI RAM indirectly. The CPU reads and writes all
12
0
Figure 16-8. QSPI Address Register (QAR)
11
0
MCF5253 Reference Manual, Rev. 1
10
0
0
9
NOTE
Description
0
8
7
0
0
6
0
5
0
4
0
3
Freescale Semiconductor
ADDR
Access: User read/write
0
2
0
1
0
0