MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 129

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8
Bus Operation
This chapter describes bus functionality, the bus control signals, and the bus cycles provided for
data-transfer operations. Bus operation is defined for transfers initiated by the MCF5253 as a bus master
and for transfers initiated by an alternate bus master. This chapter includes descriptions of the error
conditions, bus arbitration, and the reset operation.
8.1
The MCF5253 bus operates using the following features:
8.2
Although the timing of these signals is referenced to the BCLK, it is not considered a bus signal. It is
expected that the clock will be routed as needed to meet application requirements.
the MCF5253 bus signals. A brief description of the function of each signal follows.
Freescale Semiconductor
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24 bit address bus (24-bit for SDRAM access only 23-bit otherwise)
16 bit data bus
16 bit port size
Generates byte, word, longword, and line size transfers
Burst and burst-inhibited transfer support
Internal termination generation (TA)
Bus Features
Bus and Control Signals
An overbar indicates an active-low signal.
CS1/QSPI_CS3/GPIO28
Signal Name
CS0/CS4
D[31:16]
A[24:1]
RW
OE
Table 8-1. MCF5253 Bus Signal Summary
MCF5253 Reference Manual, Rev. 1
Direction
In/Out
NOTE
Out
Out
Out
Out
Out
Chip select 0 / Chip select 4
Read-write control
Output enable
Chip select 1
Description
Address bus
Data bus
Table 8-1
summarizes
8-1