MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 239

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

14.4.6
The 8-bit DMA status register (DSR) indicates the status of the DMA controller module. The DMA
controller module, in response to an event, writes to the appropriate bit in the DSR. Only a write to the
DONE bit (DSR[0]) results in action. Setting the DONE bit creates a single-cycle pulse which resets the
channel, thus clearing all bits in the register. The DONE bit is set at the completion of a transfer or during
the transfer to abort the access.
Table 14-9
Freescale Semiconductor
START
DSIZE
18–17
Address MBAR + $310
Field
15–0
16
Reset
W
R
The Destination Size field determines the data size of the destination bus cycle for the DMA controller module.
Table 14-11
Start transfer.
0 DMA inactive.
1 The DMA begins the transfer in accordance to the values in the control registers. This bit is self-clearing after one
Reserved.
MBAR + $350
MBAR + $390
MBAR + $3D0
shows the detailed structure of the DMA status register.
clock and is always read as logic 0.
DMA Status Register
–
7
Table 14-8. DMA Control Register (DCR) Field Descriptions (continued)
shows the encoding for this field.
CE
0
6
Figure 14-9. DMA Status Register (DSR)
MCF5253 Reference Manual, Rev. 1
BES
0
5
Table 14-11. DSIZE Encoding
SSize
00
01
10
11
BED
0
4
Description
Transfer Size
Longword
–
3
Word
Byte
Line
REQ
1
2
Access: User read/write
BSY
1
1
DMA Controller
DONE
1
0
14-11