MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 419

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

21.5.3
The MCF5253 model includes an IEEE 1149.1A-compliant boundary-scan register. The boundary-scan
register is connected between TDI and TDO when the EXTEST or SAMPLE/PRELOAD instructions are
selected. This register captures signal pin data on the input pins, forces fixed values on the output signal
pins, and selects the direction and drive characteristics (a logic value or high impedance) of the
bidirectional and tri-state signal pins. A detailed description of the boundary scan register bits for the
MCF5253 is part of the BDSL file.
21.5.4
The MCF5253 includes an IEEE 1149.1A-compliant bypass register, which creates a single bit shift
register path from TDI to the bypass register to TDO when the BYPASS instruction is selected.
21.6
The test logic is implemented using static logic design, and TCK can be stopped in either a high or low
state without loss of data. The system logic, however, operates on a different system clock which is not
synchronized to TCK internally. Any mixed operation requiring the use of IEEE 1149.1A test logic in
conjunction with system functional logic that uses both clocks, must have coordination and
synchronization of these clocks done externally to the MCF5253.
21.7
There are two ways to use the MCF5253 without the IEEE 1149.1A test logic being active:
There are several considerations that must be addressed if the IEEE 1149.1A logic is not going to be used
once the MCF5253 is assembled onto a board.
The prime consideration is to ensure that the IEEE 1149.1A test logic remains transparent and benign to
the system logic during functional operation. This requires the minimum of either connecting the TRST
pin to logic 0, or connecting the TCK clock pin to a clock source that will supply five rising edges and the
falling edge after the fifth rising edge, to ensure that the part enters the test-logic-reset state. The
recommended solution is to connect TRST to logic 0.
Another consideration is that the TCK pin does not have an internal pullup as is required on the TMS, TDI,
and TRST pins; therefore, it should not be left unterminated to preclude mid-level input values.
Figure 21-4
Freescale Semiconductor
1. Non-use of the JTAG test logic by either non-termination (disconnection) or intentional fixing of
2. Intentional disabling of the JTAG test logic by setting TEST[2:0]= 001 (entering Debug mode).
TAP logic values.
Restrictions
Disabling IEEE 1149.1A Standard Operation
JTAG Boundary Scan Register
JTAG Bypass Register
shows pin values recommended for disabling JTAG with the MCF5253 in JTAG mode.
MCF5253 Reference Manual, Rev. 1
IEEE 1149.1 Test Access Port (JTAG)
21-9