MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 507

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

24.7
The USB module can be broken down into functional sub-blocks described below.
24.7.1
The DMA Engine interfaces internally to dedicated DMA cache memory and has no access to main
memory. It is responsible for moving all of the data to be transferred over the USB between the module
and buffers in DMA cache memory. Like the system interface block the DMA engine block uses a simple
synchronous bus signaling protocol.
Freescale Semiconductor
Field
15–8
RXE
RXR
RXD
RXS
TXS
RXT
RXI
3–2
16
7
6
5
4
1
0
Table 24-36. Endpoint Control 1 to 3 (ENDPTCTRLn) Register Field Descriptions (continued)
TX endpoint stall. This bit will be set automatically upon receipt of a SETUP request if this Endpoint is not configured
as a Control Endpoint. It will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured
as a Control Endpoint.
The software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue
to returning STALL until this bit is either cleared by the software or automatically cleared as above.
1 Endpoint Stalled
0 Endpoint OK
Reserved.
RX endpoint enable.
1 Enabled
0 Disabled
RX data toggle reset. Whenever a configuration event is received for this Endpoint, the software must write a one to
this bit in order to synchronize the data PID’s between the Host and device.
RX data toggle inhibit. This bit is used for test only and should always be written as zero. Writing a one to this bit will
cause this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.
1 PID Sequencing Enabled
0 PID Sequencing Disabled
Reserved.
RX endpoint type.
00 Control
01 Isochronous
10 Bulk
11 Interrupt
Note: When only one endpoint (RX or TX, but not both) of an endpoint pair is used, the unused endpoint should be
configured as a bulk type endpoint.
RX endpoint data sink. This bit should always be written as 0, which selects the Dual Port Memory/DMA Engine as
the sink.
RX endpoint stall. This bit will be set automatically upon receipt of a SETUP request if this Endpoint is not configured
as a Control Endpoint. It will be cleared automatically upon receipt a SETUP request if this Endpoint is configured as
a Control Endpoint,
The software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. It will continue
to returning STALL until this bit is either cleared by the software or automatically cleared as above,
1 Endpoint Stalled
0 Endpoint OK
Functional Description
DMA Engine
MCF5253 Reference Manual, Rev. 1
Description
Universal Serial Bus Interface
24-45