MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 549

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Note that the only valid adjustment the host controller may make to C_Page is to increment by one.
24.9.10.2 Adding Interrupt Queue Heads to the Periodic Schedule
The link path(s) from the periodic frame list to a queue head establishes in which frames a transaction can
be executed for the queue head. Queue heads are linked into the periodic schedule so they are polled at the
appropriate rate. The system software sets a bit in a queue head's S-Mask to indicate which micro-frame
within a 1 millisecond period a transaction should be executed for the queue head. The software must
ensure that all queue heads in the periodic schedule have S-Mask set to a non-zero value. An S-mask with
a zero value in the context of the periodic schedule yields undefined results.
If the desired poll rate is greater than one frame, the system software can use a combination of queue head
linking and S-Mask values to spread interrupts of equal poll rates through the schedule so that the periodic
bandwidth is allocated and managed in the most efficient manner possible. Some examples are illustrated
in
24.9.10.3 Managing Transfer Complete Interrupts from Queue Heads
The host controller sets an interrupt to be signaled at the next interrupt threshold when the completed
transfer (qTD) has an Interrupt on Complete (IOC) bit set, or whenever a transfer (qTD) completes with a
short packet. If the system software needs multiple qTDs to complete a client request (that is, like a control
transfer) the intermediate qTDs do not require interrupts. The system software may only need a single
interrupt to notify it that the complete buffer has been transferred. The system software may set IOC's to
occur more frequently. A motivation for this may be that it wants early notification so that interface data
structures can be re-used in a timely manner.
Freescale Semiconductor
0, 2, 4, 6, 8,....
S-Mask = 0x01
0, 2, 4, 6, 8,...
S-Mask = 0x02
Table
Reference
Sequence
•
•
•
Frame #
The current transaction does not span a page boundary. The value of C_Page is not adjusted by the
host controller.
The current transaction does span a page boundary. The host controller must detect the page cross
condition and advance to the next buffer while streaming data to/from the USB.
The current transaction completes on a page boundary (that is, the last byte moved for the current
transaction is the last byte in the page for the current page pointer). The host controller must
increment C_Page before writing back status for the transaction.
24-65.
A queue head for the bInterval of 2 milliseconds (16 micro-frames) is linked into the periodic schedule so that
it is reachable from the periodic frame list locations indicated in the previous column. In addition, the S-Mask
field in the queue head is set to 0x01, indicating that the transaction for the endpoint should be executed on
the bus during micro-frame 0 of the frame.
Another example of a queue head with a bInterval of 2 milliseconds is linked into the periodic frame list at
exactly the same interval as the previous example. However, the S-Mask is set to 0x02 indicating that the
transaction for the endpoint should be executed on the bus during micro-frame 1 of the frame.
Table 24-65. Example Periodic Reference Patterns for Interrupt Transfers
MCF5253 Reference Manual, Rev. 1
Description
Universal Serial Bus Interface
24-87