MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 270

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

UART Modules
15.4.8
The UIPCR registers show the current state and the change-of-state for the CTS pin. (Note: not available
on UART2).
15.4.9
The UART auxiliary control registers control the input enable.
15-24
Field
COS
Address MBAR + $1D0 (UIPCR0)
7–5,
CTS
3–1
4
0
Bit Name
TB7–TB0
Reset
W
R
Reserved
1 A change-of-state (high-to-low or low-to-high transition), lasting longer than 25–50 μs has occurred at the CTS input.
0 No change-of-state has occurred since the last time the CPU read the UART Input Port Change Register (UIPCR).
Current State
Starting two serial clock periods after reset, the CTS bit reflects the state of the CTS pin. If the CTS pin is detected as
asserted at that time, the COS bit is set, which initiates an interrupt if the Input Enable Control (IEC) bit of the UACR
register is enabled.
1 The current state of the CTS input is logic one.
0 The current state of the CTS input is logic zero.
Note: Not available on UART2
Change-of-State
MBAR + $210 (UIPCR1)
MBAR2 + $C10 (UIPCR2)
When this bit is set, the UART Auxiliary Control Register (UACR) can be programmed to generate an interrupt to
the CPU.
A read of the UIPCR also clears the UART Interrupt Status Register (UISR)COS bit.
Input Port Change Registers (UIPCRn)
Auxiliary Control Registers (UACRn)
7
0
These bits contain the character in the transmitter buffer.
Table 15-14. Input Port Change Register (UIPCRn) Field Descriptions
Table 15-13. Transmitter Buffer (UTBn) Register Field Descriptions
0
6
Figure 15-15. Input Port Change Register (UIPCRn)
MCF5253 Reference Manual, Rev. 1
5
0
COS
0
4
Description
Description
1
3
1
2
Freescale Semiconductor
Access: User read only
1
1
CTS
1
0